diff --git a/litex_boards/platforms/orangecrab.py b/litex_boards/platforms/orangecrab.py index f2c6b09..071460c 100644 --- a/litex_boards/platforms/orangecrab.py +++ b/litex_boards/platforms/orangecrab.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2019 Greg Davill +# This file is Copyright (c) Greg Davill # License: BSD from litex.build.generic_platform import * @@ -6,20 +6,15 @@ from litex.build.lattice import LatticePlatform # IOs ---------------------------------------------------------------------------------------------- -_io = [ +_io_r0_1 = [ ("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")), ("rgb_led", 0, - Subsignal("r", Pins("V17"), IOStandard("LVCMOS25")), - Subsignal("g", Pins("T17"), IOStandard("LVCMOS25")), + Subsignal("r", Pins("V17"), IOStandard("LVCMOS33")), + Subsignal("g", Pins("T17"), IOStandard("LVCMOS33")), Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")), ), - ("serial", 0, - Subsignal("tx", Pins("N17"), IOStandard("LVCMOS25")), - Subsignal("rx", Pins("M18"), IOStandard("LVCMOS25")), - ), - ("ddram", 0, Subsignal("a", Pins( "A4 D2 C3 C7 D3 D4 D1 B2", @@ -48,15 +43,125 @@ _io = [ Subsignal("cs_n", Pins("U17")), Subsignal("clk", Pins("U16")), Subsignal("dq", Pins("U18", "T18", "R18", "N18")), - IOStandard("LVCMOS25") + IOStandard("LVCMOS33") + ), + + ("spi-internal", 0, + Subsignal("cs_n", Pins("B11"), Misc("PULLMODE=UP")), + Subsignal("clk", Pins("C11")), + Subsignal("miso", Pins("A11"), Misc("PULLMODE=UP")), + Subsignal("mosi", Pins("A10"), Misc("PULLMODE=UP")), + IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW") ), ] +_io_r0_2 = [ + ("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")), + ("rst_n", 0, Pins("V17"), IOStandard("LVCMOS33")), + + ("usr_btn", 0, Pins("J17"),IOStandard("SSTL135_I")), + + ("rgb_led", 0, + Subsignal("r", Pins("K4"), IOStandard("LVCMOS33")), + Subsignal("g", Pins("M3"), IOStandard("LVCMOS33")), + Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")), + ), + + ("ddram", 0, + Subsignal("a", Pins( + "C4 D2 D3 A3 A4 D4 C3 B2", + "B1 D1 A7 C2 B6 C1 A2 C7"), + IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("ba", Pins("D6 B7 A6"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("ras_n", Pins("C12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("cas_n", Pins("D13"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("we_n", Pins("B12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("cs_n", Pins("A12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("dm", Pins("D16 G16"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("dq", Pins( + "C17 D15 B17 C16 A15 B13 A17 A13", + "F17 F16 G15 F15 J16 C18 H16 F18"), + IOStandard("SSTL135_I"), + Misc("TERMINATION=75 SLEWRATE=FAST")), + Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF DIFFRESISTOR=100 SLEWRATE=FAST")), + Subsignal("clk_p", Pins("J18"), IOStandard("SSTL135D_I"),Misc("SLEWRATE=FAST")), + Subsignal("cke", Pins("D18"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("odt", Pins("C13"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("reset_n", Pins("L18"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("vccio", Pins("K16 D17 K15 K17 B18 C6"), IOStandard("SSTL135_II")), + Subsignal("gnd", Pins("L15 L16"), IOStandard("SSTL135_II")), + ), + + ("usb", 0, + Subsignal("d_p", Pins("N1")), + Subsignal("d_n", Pins("M2")), + Subsignal("pullup", Pins("N2")), + IOStandard("LVCMOS33") + ), + + ("spiflash4x", 0, + Subsignal("cs_n", Pins("U17"), IOStandard("LVCMOS33")), + #Subsignal("clk", Pins("U16"), IOStandard("LVCMOS33")), + Subsignal("dq", Pins("U18 T18 R18 N18"), IOStandard("LVCMOS33")), + ), + ("spiflash", 0, + Subsignal("cs_n", Pins("U17"), IOStandard("LVCMOS33")), + #Subsignal("clk", Pins("U16"), IOStandard("LVCMOS33")), # Note: CLK is bound using USRMCLK block + Subsignal("miso", Pins("T18"), IOStandard("LVCMOS33")), + Subsignal("mosi", Pins("U18"), IOStandard("LVCMOS33")), + Subsignal("wp", Pins("R18"), IOStandard("LVCMOS33")), + Subsignal("hold", Pins("N18"), IOStandard("LVCMOS33")), + ), +] + +# Connectors --------------------------------------------------------------------------------------- + +_connectors_r0_1 = [ + # Feather 0.1" Header Pin Numbers, + # Note: Pin nubering is not continuous. + ("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - - - - - - - -"), +] + +_connectors_r0_2 = [ + # Feather 0.1" Header Pin Numbers, + # Note: Pin nubering is not continuous. + ("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - L4 N3 N4 H4 G4 T17"), +] + + +# Standard Feather Pins +feather_serial = [ + ("serial", 0, + Subsignal("tx", Pins("GPIO:1"), IOStandard("LVCMOS33")), + Subsignal("rx", Pins("GPIO:0"), IOStandard("LVCMOS33")) + ) +] + +feather_i2c = [ + ("i2c", 0, + ("sda", Pins("GPIO:2"), IOStandard("LVCMOS33")), + ("scl", Pins("GPIO:3"), IOStandard("LVCMOS33")) + ) +] + +feather_spi = [ + ("spi",0, + ("miso", Pins("GPIO:14"), IOStandard("LVCMOS33")), + ("mosi", Pins("GPIO:16"), IOStandard("LVCMOS33")), + ("sck", Pins("GPIO:15"), IOStandard("LVCMOS33")) + ) +] + + # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): default_clk_name = "clk48" default_clk_period = 1e9/48e6 - def __init__(self, **kwargs): - LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, **kwargs) + def __init__(self, revision="0.2", device="25F", **kwargs): + assert revision in ["0.1", "0.2"] + self.revision = revision + io = {"0.1": _io_r0_1, "0.2": _io_r0_2 }[revision] + connectors = {"0.1": _connectors_r0_1, "0.2": _connectors_r0_2}[revision] + LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", io, connectors, **kwargs) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 5a5a613..da1f917 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -17,7 +17,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litedram.modules import MT41K64M16 +from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16 from litedram.phy import ECP5DDRPHY # _CRG --------------------------------------------------------------------------------------------- @@ -57,8 +57,7 @@ class _CRG(Module): Instance("ECLKBRIDGECS", i_CLK0 = self.cd_sys2x_i.clk, i_SEL = 0, - o_ECSOUT = sys2x_clk_ecsout, - ), + o_ECSOUT = sys2x_clk_ecsout), Instance("ECLKSYNCB", i_ECLKI = sys2x_clk_ecsout, i_STOP = self.stop, @@ -77,16 +76,32 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): - platform = orangecrab.Platform(toolchain=toolchain) + # Board Revision --------------------------------------------------------------------------- + revision = kwargs.get("revision", "0.2") + device = kwargs.get("device", "25F") + platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) + + # Serial ----------------------------------------------------------------------------------- + platform.add_extension(orangecrab.feather_serial) - # SoCCore ----------------------------------------------------------------_----------------- + # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) + # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: + available_sdram_modules = { + 'MT41K64M16': MT41K64M16, + 'MT41K128M16': MT41K128M16, + 'MT41K256M16': MT41K256M16, +# 'MT41K512M16': MT41K512M16 + } + sdram_module = available_sdram_modules.get( + kwargs.get("sdram_device", "MT41K64M16")) + self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) @@ -95,7 +110,7 @@ class BaseSoC(SoCCore): self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.add_sdram("sdram", phy = self.ddrphy, - module = MT41K64M16(sys_clk_freq, "1:2"), + module = sdram_module(sys_clk_freq, "1:2"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), @@ -114,6 +129,12 @@ def main(): trellis_args(parser) parser.add_argument("--sys-clk-freq", default=48e6, help="system clock frequency (default=48MHz)") + parser.add_argument("--revision", default="0.2", + help="Board Revision {0.1, 0.2} (default=0.2)") + parser.add_argument("--device", default="25F", + help="ECP5 device (default=25F)") + parser.add_argument("--sdram-device", default="MT41K64M16", + help="ECP5 device (default=MT41K64M16)") args = parser.parse_args() soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))