From 88d3f1d63e6bcddeb17f89cd0ca05a17f0d525df Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Sun, 22 Mar 2020 20:14:29 +1030 Subject: [PATCH 1/6] orangecrab: r0.1 OrangeCrab fixes --- litex_boards/platforms/orangecrab.py | 57 ++++++++++++++++++++++------ litex_boards/targets/orangecrab.py | 11 ++++-- 2 files changed, 54 insertions(+), 14 deletions(-) diff --git a/litex_boards/platforms/orangecrab.py b/litex_boards/platforms/orangecrab.py index f2c6b09..913988e 100644 --- a/litex_boards/platforms/orangecrab.py +++ b/litex_boards/platforms/orangecrab.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2019 Greg Davill +# This file is Copyright (c) Greg Davill # License: BSD from litex.build.generic_platform import * @@ -10,16 +10,11 @@ _io = [ ("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")), ("rgb_led", 0, - Subsignal("r", Pins("V17"), IOStandard("LVCMOS25")), - Subsignal("g", Pins("T17"), IOStandard("LVCMOS25")), + Subsignal("r", Pins("V17"), IOStandard("LVCMOS33")), + Subsignal("g", Pins("T17"), IOStandard("LVCMOS33")), Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")), ), - ("serial", 0, - Subsignal("tx", Pins("N17"), IOStandard("LVCMOS25")), - Subsignal("rx", Pins("M18"), IOStandard("LVCMOS25")), - ), - ("ddram", 0, Subsignal("a", Pins( "A4 D2 C3 C7 D3 D4 D1 B2", @@ -48,15 +43,55 @@ _io = [ Subsignal("cs_n", Pins("U17")), Subsignal("clk", Pins("U16")), Subsignal("dq", Pins("U18", "T18", "R18", "N18")), - IOStandard("LVCMOS25") + IOStandard("LVCMOS33") + ), + + ("spi-internal", 0, + Subsignal("cs_n", Pins("B11"), Misc("PULLMODE=UP")), + Subsignal("clk", Pins("C11")), + Subsignal("miso", Pins("A11"), Misc("PULLMODE=UP")), + Subsignal("mosi", Pins("A10"), Misc("PULLMODE=UP")), + IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW") ), ] +# Connectors --------------------------------------------------------------------------------------- + +_connectors = [ + # Feather 0.1" Header Pin Numbers, + # Note: Pin nubering is not continuous. + ("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - - - - - - - -"), +] + +# Standard Feather Pins +feather_serial = [ + ("serial", 0, + Subsignal("tx", Pins("GPIO:1"), IOStandard("LVCMOS33")), + Subsignal("rx", Pins("GPIO:0"), IOStandard("LVCMOS33")) + ) +] + +feather_i2c = [ + ("i2c", 0, + ("sda", Pins("GPIO:2"), IOStandard("LVCMOS33")), + ("scl", Pins("GPIO:3"), IOStandard("LVCMOS33")) + ) +] + +feather_spi = [ + ("spi",0, + ("miso", Pins("GPIO:14"), IOStandard("LVCMOS33")), + ("mosi", Pins("GPIO:16"), IOStandard("LVCMOS33")), + ("sck", Pins("GPIO:15"), IOStandard("LVCMOS33")) + ) +] + + # Platform ----------------------------------------------------------------------------------------- class Platform(LatticePlatform): default_clk_name = "clk48" default_clk_period = 1e9/48e6 - def __init__(self, **kwargs): - LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, **kwargs) + def __init__(self, device='25F', **kwargs): + LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", _io, _connectors, **kwargs) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 5a5a613..14528d5 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -57,8 +57,7 @@ class _CRG(Module): Instance("ECLKBRIDGECS", i_CLK0 = self.cd_sys2x_i.clk, i_SEL = 0, - o_ECSOUT = sys2x_clk_ecsout, - ), + o_ECSOUT = sys2x_clk_ecsout), Instance("ECLKSYNCB", i_ECLKI = sys2x_clk_ecsout, i_STOP = self.stop, @@ -78,13 +77,17 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): platform = orangecrab.Platform(toolchain=toolchain) + + # Serial ----------------------------------------------------------------------------------- + platform.add_extension(orangecrab.feather_serial) - # SoCCore ----------------------------------------------------------------_----------------- + # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) + # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = ECP5DDRPHY( @@ -114,6 +117,8 @@ def main(): trellis_args(parser) parser.add_argument("--sys-clk-freq", default=48e6, help="system clock frequency (default=48MHz)") + parser.add_argument("--device", default="25F", + help="ECP5 device (default=25F)") args = parser.parse_args() soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) From bf3c9dc9bf97e3aa99d5db9ed1cae88878a13d49 Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Sun, 22 Mar 2020 20:41:12 +1030 Subject: [PATCH 2/6] orangecrab: Add sdram selection option --- litex_boards/targets/orangecrab.py | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 14528d5..e2702db 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -17,7 +17,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litedram.modules import MT41K64M16 +from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16 from litedram.phy import ECP5DDRPHY # _CRG --------------------------------------------------------------------------------------------- @@ -90,6 +90,15 @@ class BaseSoC(SoCCore): # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: + available_sdram_modules = { + 'MT41K64M16': MT41K64M16, + 'MT41K128M16': MT41K128M16, + 'MT41K256M16': MT41K256M16, +# 'MT41K512M16': MT41K512M16 + } + sdram_module = available_sdram_modules.get( + kwargs.get("sdram_device", "MT41K64M16")) + self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) @@ -98,7 +107,7 @@ class BaseSoC(SoCCore): self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.add_sdram("sdram", phy = self.ddrphy, - module = MT41K64M16(sys_clk_freq, "1:2"), + module = sdram_module(sys_clk_freq, "1:2"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), @@ -119,6 +128,8 @@ def main(): help="system clock frequency (default=48MHz)") parser.add_argument("--device", default="25F", help="ECP5 device (default=25F)") + parser.add_argument("--sdram-device", default="MT41K64M16", + help="ECP5 device (default=MT41K64M16)") args = parser.parse_args() soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) From 159360da2cd83babcd451f4e081190d6fe69b712 Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Sun, 22 Mar 2020 21:04:07 +1030 Subject: [PATCH 3/6] orangecrab: Add r0.2 support --- .../{orangecrab.py => orangecrab_r0_1.py} | 0 litex_boards/platforms/orangecrab_r0_2.py | 107 ++++++++++++++++++ litex_boards/targets/orangecrab.py | 11 +- 3 files changed, 117 insertions(+), 1 deletion(-) rename litex_boards/platforms/{orangecrab.py => orangecrab_r0_1.py} (100%) create mode 100644 litex_boards/platforms/orangecrab_r0_2.py diff --git a/litex_boards/platforms/orangecrab.py b/litex_boards/platforms/orangecrab_r0_1.py similarity index 100% rename from litex_boards/platforms/orangecrab.py rename to litex_boards/platforms/orangecrab_r0_1.py diff --git a/litex_boards/platforms/orangecrab_r0_2.py b/litex_boards/platforms/orangecrab_r0_2.py new file mode 100644 index 0000000..7aef6aa --- /dev/null +++ b/litex_boards/platforms/orangecrab_r0_2.py @@ -0,0 +1,107 @@ +# This file is Copyright (c) Greg Davill +# License: BSD + +from litex.build.generic_platform import * +from litex.build.lattice import LatticePlatform + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + ("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")), + ("rst_n", 0, Pins("V17"), IOStandard("LVCMOS33")), + + ("usr_btn", 0, Pins("J17"),IOStandard("SSTL135_I")), + + ("rgb_led", 0, + Subsignal("r", Pins("K4"), IOStandard("LVCMOS33")), + Subsignal("g", Pins("M3"), IOStandard("LVCMOS33")), + Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")), + ), + + ("ddram", 0, + Subsignal("a", Pins( + "C4 D2 D3 A3 A4 D4 C3 B2", + "B1 D1 A7 C2 B6 C1 A2 C7"), + IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("ba", Pins("D6 B7 A6"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("ras_n", Pins("C12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("cas_n", Pins("D13"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("we_n", Pins("B12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("cs_n", Pins("A12"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("dm", Pins("D16 G16"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("dq", Pins( + "C17 D15 B17 C16 A15 B13 A17 A13", + "F17 F16 G15 F15 J16 C18 H16 F18"), + IOStandard("SSTL135_I"), + Misc("TERMINATION=75 SLEWRATE=FAST")), + Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF DIFFRESISTOR=100 SLEWRATE=FAST")), + Subsignal("clk_p", Pins("J18"), IOStandard("SSTL135D_I"),Misc("SLEWRATE=FAST")), + Subsignal("cke", Pins("D18"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("odt", Pins("C13"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("reset_n", Pins("L18"), IOStandard("SSTL135_I"),Misc("SLEWRATE=FAST")), + Subsignal("vccio", Pins("K16 D17 K15 K17 B18 C6"), IOStandard("SSTL135_II")), + Subsignal("gnd", Pins("L15 L16"), IOStandard("SSTL135_II")), + ), + + ("usb", 0, + Subsignal("d_p", Pins("N1")), + Subsignal("d_n", Pins("M2")), + Subsignal("pullup", Pins("N2")), + IOStandard("LVCMOS33") + ), + + ("spiflash4x", 0, + Subsignal("cs_n", Pins("U17"), IOStandard("LVCMOS33")), + #Subsignal("clk", Pins("U16"), IOStandard("LVCMOS33")), + Subsignal("dq", Pins("U18 T18 R18 N18"), IOStandard("LVCMOS33")), + ), + ("spiflash", 0, + Subsignal("cs_n", Pins("U17"), IOStandard("LVCMOS33")), + #Subsignal("clk", Pins("U16"), IOStandard("LVCMOS33")), # Note: CLK is bound using USRMCLK block + Subsignal("miso", Pins("T18"), IOStandard("LVCMOS33")), + Subsignal("mosi", Pins("U18"), IOStandard("LVCMOS33")), + Subsignal("wp", Pins("R18"), IOStandard("LVCMOS33")), + Subsignal("hold", Pins("N18"), IOStandard("LVCMOS33")), + ), +] + +# Connectors --------------------------------------------------------------------------------------- + +_connectors = [ + # Feather 0.1" Header Pin Numbers, + # Note: Pin nubering is not continuous. + ("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - L4 N3 N4 H4 G4 T17"), +] + +# Standard Feather Pins +feather_serial = [ + ("serial", 0, + Subsignal("tx", Pins("GPIO:1"), IOStandard("LVCMOS33")), + Subsignal("rx", Pins("GPIO:0"), IOStandard("LVCMOS33")) + ) +] + +feather_i2c = [ + ("i2c", 0, + ("sda", Pins("GPIO:2"), IOStandard("LVCMOS33")), + ("scl", Pins("GPIO:3"), IOStandard("LVCMOS33")) + ) +] + +feather_spi = [ + ("spi",0, + ("miso", Pins("GPIO:14"), IOStandard("LVCMOS33")), + ("mosi", Pins("GPIO:16"), IOStandard("LVCMOS33")), + ("sck", Pins("GPIO:15"), IOStandard("LVCMOS33")) + ) +] + + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(LatticePlatform): + default_clk_name = "clk48" + default_clk_period = 1e9/48e6 + + def __init__(self, device='25F', **kwargs): + LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", _io, _connectors, **kwargs) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index e2702db..7779714 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -8,7 +8,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import orangecrab +from litex_boards.platforms import orangecrab_r0_1, orangecrab_r0_2 from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -76,6 +76,13 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): + # Board Revision --------------------------------------------------------------------------- + revision = kwargs.get("revision", "r0.2") + boards = { + 'r0.1': orangecrab_r0_1, + 'r0.2': orangecrab_r0_2 + } + orangecrab = boards.get(revision) platform = orangecrab.Platform(toolchain=toolchain) # Serial ----------------------------------------------------------------------------------- @@ -126,6 +133,8 @@ def main(): trellis_args(parser) parser.add_argument("--sys-clk-freq", default=48e6, help="system clock frequency (default=48MHz)") + parser.add_argument("--revision", default="r0.2", + help="Board Revision {r0.1, r0.2} (default=r0.2)") parser.add_argument("--device", default="25F", help="ECP5 device (default=25F)") parser.add_argument("--sdram-device", default="MT41K64M16", From 357aeac59d447a3d7581d40175a9b81d667d6637 Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Sun, 22 Mar 2020 21:25:39 +1030 Subject: [PATCH 4/6] test_targets: Update orangecrab platforms --- test/test_targets.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/test/test_targets.py b/test/test_targets.py index 0ff2d03..4d5d180 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -90,7 +90,8 @@ class TestTargets(unittest.TestCase): # Lattice ECP5 platforms.append("ecp5_evn") platforms.append("hadbadge") - platforms.append("orangecrab") + platforms.append("orangecrab_r0_1") + platforms.append("orangecrab_r0_2") platforms.append("trellisboard") platforms.append("ulx3s") platforms.append("versa_ecp5") From eb35ec92bafd2cf31553a492062d766529c43e39 Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Mon, 23 Mar 2020 09:20:01 +1030 Subject: [PATCH 5/6] orangecrab: combine revisions in target --- .../{orangecrab_r0_2.py => orangecrab.py} | 68 ++++++++++++- litex_boards/platforms/orangecrab_r0_1.py | 97 ------------------- litex_boards/targets/orangecrab.py | 16 ++- 3 files changed, 70 insertions(+), 111 deletions(-) rename litex_boards/platforms/{orangecrab_r0_2.py => orangecrab.py} (62%) delete mode 100644 litex_boards/platforms/orangecrab_r0_1.py diff --git a/litex_boards/platforms/orangecrab_r0_2.py b/litex_boards/platforms/orangecrab.py similarity index 62% rename from litex_boards/platforms/orangecrab_r0_2.py rename to litex_boards/platforms/orangecrab.py index 7aef6aa..071460c 100644 --- a/litex_boards/platforms/orangecrab_r0_2.py +++ b/litex_boards/platforms/orangecrab.py @@ -6,7 +6,56 @@ from litex.build.lattice import LatticePlatform # IOs ---------------------------------------------------------------------------------------------- -_io = [ +_io_r0_1 = [ + ("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")), + + ("rgb_led", 0, + Subsignal("r", Pins("V17"), IOStandard("LVCMOS33")), + Subsignal("g", Pins("T17"), IOStandard("LVCMOS33")), + Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")), + ), + + ("ddram", 0, + Subsignal("a", Pins( + "A4 D2 C3 C7 D3 D4 D1 B2", + "C1 A2 A7 C2 C4"), + IOStandard("SSTL135_I")), + Subsignal("ba", Pins("B6 B7 A6"), IOStandard("SSTL135_I")), + Subsignal("ras_n", Pins("C12"), IOStandard("SSTL135_I")), + Subsignal("cas_n", Pins("D13"), IOStandard("SSTL135_I")), + Subsignal("we_n", Pins("B12"), IOStandard("SSTL135_I")), + Subsignal("cs_n", Pins("A12"), IOStandard("SSTL135_I")), + Subsignal("dm", Pins("D16 G16"), IOStandard("SSTL135_I")), + Subsignal("dq", Pins( + "C17 D15 B17 C16 A15 B13 A17 A13", + "F17 F16 G15 F15 J16 C18 H16 F18"), + IOStandard("SSTL135_I"), + Misc("TERMINATION=75")), + Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF DIFFRESISTOR=100")), + Subsignal("clk_p", Pins("J18"), IOStandard("SSTL135D_I")), + Subsignal("cke", Pins("D6"), IOStandard("SSTL135_I")), + Subsignal("odt", Pins("C13"), IOStandard("SSTL135_I")), + Subsignal("reset_n", Pins("B1"), IOStandard("SSTL135_I")), + Misc("SLEWRATE=FAST") + ), + + ("spiflash4x", 0, + Subsignal("cs_n", Pins("U17")), + Subsignal("clk", Pins("U16")), + Subsignal("dq", Pins("U18", "T18", "R18", "N18")), + IOStandard("LVCMOS33") + ), + + ("spi-internal", 0, + Subsignal("cs_n", Pins("B11"), Misc("PULLMODE=UP")), + Subsignal("clk", Pins("C11")), + Subsignal("miso", Pins("A11"), Misc("PULLMODE=UP")), + Subsignal("mosi", Pins("A10"), Misc("PULLMODE=UP")), + IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW") + ), +] + +_io_r0_2 = [ ("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")), ("rst_n", 0, Pins("V17"), IOStandard("LVCMOS33")), @@ -67,12 +116,19 @@ _io = [ # Connectors --------------------------------------------------------------------------------------- -_connectors = [ +_connectors_r0_1 = [ + # Feather 0.1" Header Pin Numbers, + # Note: Pin nubering is not continuous. + ("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - - - - - - - -"), +] + +_connectors_r0_2 = [ # Feather 0.1" Header Pin Numbers, # Note: Pin nubering is not continuous. ("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - L4 N3 N4 H4 G4 T17"), ] + # Standard Feather Pins feather_serial = [ ("serial", 0, @@ -103,5 +159,9 @@ class Platform(LatticePlatform): default_clk_name = "clk48" default_clk_period = 1e9/48e6 - def __init__(self, device='25F', **kwargs): - LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", _io, _connectors, **kwargs) + def __init__(self, revision="0.2", device="25F", **kwargs): + assert revision in ["0.1", "0.2"] + self.revision = revision + io = {"0.1": _io_r0_1, "0.2": _io_r0_2 }[revision] + connectors = {"0.1": _connectors_r0_1, "0.2": _connectors_r0_2}[revision] + LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", io, connectors, **kwargs) diff --git a/litex_boards/platforms/orangecrab_r0_1.py b/litex_boards/platforms/orangecrab_r0_1.py deleted file mode 100644 index 913988e..0000000 --- a/litex_boards/platforms/orangecrab_r0_1.py +++ /dev/null @@ -1,97 +0,0 @@ -# This file is Copyright (c) Greg Davill -# License: BSD - -from litex.build.generic_platform import * -from litex.build.lattice import LatticePlatform - -# IOs ---------------------------------------------------------------------------------------------- - -_io = [ - ("clk48", 0, Pins("A9"), IOStandard("LVCMOS33")), - - ("rgb_led", 0, - Subsignal("r", Pins("V17"), IOStandard("LVCMOS33")), - Subsignal("g", Pins("T17"), IOStandard("LVCMOS33")), - Subsignal("b", Pins("J3"), IOStandard("LVCMOS33")), - ), - - ("ddram", 0, - Subsignal("a", Pins( - "A4 D2 C3 C7 D3 D4 D1 B2", - "C1 A2 A7 C2 C4"), - IOStandard("SSTL135_I")), - Subsignal("ba", Pins("B6 B7 A6"), IOStandard("SSTL135_I")), - Subsignal("ras_n", Pins("C12"), IOStandard("SSTL135_I")), - Subsignal("cas_n", Pins("D13"), IOStandard("SSTL135_I")), - Subsignal("we_n", Pins("B12"), IOStandard("SSTL135_I")), - Subsignal("cs_n", Pins("A12"), IOStandard("SSTL135_I")), - Subsignal("dm", Pins("D16 G16"), IOStandard("SSTL135_I")), - Subsignal("dq", Pins( - "C17 D15 B17 C16 A15 B13 A17 A13", - "F17 F16 G15 F15 J16 C18 H16 F18"), - IOStandard("SSTL135_I"), - Misc("TERMINATION=75")), - Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF DIFFRESISTOR=100")), - Subsignal("clk_p", Pins("J18"), IOStandard("SSTL135D_I")), - Subsignal("cke", Pins("D6"), IOStandard("SSTL135_I")), - Subsignal("odt", Pins("C13"), IOStandard("SSTL135_I")), - Subsignal("reset_n", Pins("B1"), IOStandard("SSTL135_I")), - Misc("SLEWRATE=FAST") - ), - - ("spiflash4x", 0, - Subsignal("cs_n", Pins("U17")), - Subsignal("clk", Pins("U16")), - Subsignal("dq", Pins("U18", "T18", "R18", "N18")), - IOStandard("LVCMOS33") - ), - - ("spi-internal", 0, - Subsignal("cs_n", Pins("B11"), Misc("PULLMODE=UP")), - Subsignal("clk", Pins("C11")), - Subsignal("miso", Pins("A11"), Misc("PULLMODE=UP")), - Subsignal("mosi", Pins("A10"), Misc("PULLMODE=UP")), - IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW") - ), -] - -# Connectors --------------------------------------------------------------------------------------- - -_connectors = [ - # Feather 0.1" Header Pin Numbers, - # Note: Pin nubering is not continuous. - ("GPIO", "N17 M18 C10 C9 - B10 B9 - - C8 B8 A8 H2 J2 N15 R17 N16 - - - - - - - -"), -] - -# Standard Feather Pins -feather_serial = [ - ("serial", 0, - Subsignal("tx", Pins("GPIO:1"), IOStandard("LVCMOS33")), - Subsignal("rx", Pins("GPIO:0"), IOStandard("LVCMOS33")) - ) -] - -feather_i2c = [ - ("i2c", 0, - ("sda", Pins("GPIO:2"), IOStandard("LVCMOS33")), - ("scl", Pins("GPIO:3"), IOStandard("LVCMOS33")) - ) -] - -feather_spi = [ - ("spi",0, - ("miso", Pins("GPIO:14"), IOStandard("LVCMOS33")), - ("mosi", Pins("GPIO:16"), IOStandard("LVCMOS33")), - ("sck", Pins("GPIO:15"), IOStandard("LVCMOS33")) - ) -] - - -# Platform ----------------------------------------------------------------------------------------- - -class Platform(LatticePlatform): - default_clk_name = "clk48" - default_clk_period = 1e9/48e6 - - def __init__(self, device='25F', **kwargs): - LatticePlatform.__init__(self, f"LFE5U-{device}-8MG285C", _io, _connectors, **kwargs) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 7779714..da1f917 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -8,7 +8,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import orangecrab_r0_1, orangecrab_r0_2 +from litex_boards.platforms import orangecrab from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -77,13 +77,9 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): # Board Revision --------------------------------------------------------------------------- - revision = kwargs.get("revision", "r0.2") - boards = { - 'r0.1': orangecrab_r0_1, - 'r0.2': orangecrab_r0_2 - } - orangecrab = boards.get(revision) - platform = orangecrab.Platform(toolchain=toolchain) + revision = kwargs.get("revision", "0.2") + device = kwargs.get("device", "25F") + platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) # Serial ----------------------------------------------------------------------------------- platform.add_extension(orangecrab.feather_serial) @@ -133,8 +129,8 @@ def main(): trellis_args(parser) parser.add_argument("--sys-clk-freq", default=48e6, help="system clock frequency (default=48MHz)") - parser.add_argument("--revision", default="r0.2", - help="Board Revision {r0.1, r0.2} (default=r0.2)") + parser.add_argument("--revision", default="0.2", + help="Board Revision {0.1, 0.2} (default=0.2)") parser.add_argument("--device", default="25F", help="ECP5 device (default=25F)") parser.add_argument("--sdram-device", default="MT41K64M16", From fe2fa097fa6a7829b79345321eee19c8d070739a Mon Sep 17 00:00:00 2001 From: Greg Davill Date: Mon, 23 Mar 2020 09:20:41 +1030 Subject: [PATCH 6/6] test_targets: revert orangecrab test build --- test/test_targets.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/test/test_targets.py b/test/test_targets.py index 4d5d180..0ff2d03 100644 --- a/test/test_targets.py +++ b/test/test_targets.py @@ -90,8 +90,7 @@ class TestTargets(unittest.TestCase): # Lattice ECP5 platforms.append("ecp5_evn") platforms.append("hadbadge") - platforms.append("orangecrab_r0_1") - platforms.append("orangecrab_r0_2") + platforms.append("orangecrab") platforms.append("trellisboard") platforms.append("ulx3s") platforms.append("versa_ecp5")