From 1333f89ed6b8642dc6ea238ab80860cb0088cc10 Mon Sep 17 00:00:00 2001 From: alainlou Date: Wed, 22 Sep 2021 00:07:55 -0400 Subject: [PATCH] rz_easyfpga: adjust SDRAM clk phase - also add 1:2 rate --- litex_boards/platforms/rz_easyfpga.py | 3 --- litex_boards/targets/rz_easyfpga.py | 32 ++++++++++++++++++--------- 2 files changed, 22 insertions(+), 13 deletions(-) diff --git a/litex_boards/platforms/rz_easyfpga.py b/litex_boards/platforms/rz_easyfpga.py index 7c17b15..10603f0 100644 --- a/litex_boards/platforms/rz_easyfpga.py +++ b/litex_boards/platforms/rz_easyfpga.py @@ -28,8 +28,6 @@ _io = [ ), # SDRAM - # It may help to add a header cable to some pins to mitigate suspected electrical problems on the board - # (especially pin 67, but adding cables to the whole addr bus seemed to be the most robust) ("sdram_clock", 0, Pins("43"), IOStandard("3.3-V LVTTL")), ("sdram", 0, Subsignal("a", Pins( @@ -49,7 +47,6 @@ _io = [ ), ] - # Platform ----------------------------------------------------------------------------------------- class Platform(AlteraPlatform): diff --git a/litex_boards/targets/rz_easyfpga.py b/litex_boards/targets/rz_easyfpga.py index 1286c23..8934efb 100755 --- a/litex_boards/targets/rz_easyfpga.py +++ b/litex_boards/targets/rz_easyfpga.py @@ -20,15 +20,19 @@ from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser from litedram.modules import MT48LC4M16 -from litedram.phy import GENSDRPHY +from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform, sys_clk_freq): + def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) + if sdram_rate == "1:2": + self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) + else: + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # @@ -40,15 +44,20 @@ class _CRG(Module): self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + if sdram_rate == "1:2": + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=270) # Ideally 90° but needs to be increased. + else: + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Ideally 90° but needs to be increased. # SDRAM clock - self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(25e6), with_led_chaser=True, **kwargs): + def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, sdram_rate="1:1", **kwargs): platform = easyfpga.Platform() # Limit internal rom and sram size @@ -62,14 +71,15 @@ class BaseSoC(SoCCore): **kwargs) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) + sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, - module = MT48LC4M16(sys_clk_freq, "1:1"), # Hynix HY57V641620FTP-7 + module = MT48LC4M16(sys_clk_freq, sdram_rate), # Hynix HY57V641620FTP-7 l2_cache_size = 0 ) @@ -85,13 +95,15 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on RZ-EasyFPGA") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 25MHz)") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), + sdram_rate = args.sdram_rate, **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args))