diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py index 0eaaab8..dd60861 100755 --- a/litex_boards/targets/ecpix5.py +++ b/litex_boards/targets/ecpix5.py @@ -35,7 +35,8 @@ class _CRG(Module): # # # - self.stop = Signal() + self.stop = Signal() + self.reset = Signal() # Clk / Rst clk100 = platform.request("clk100") @@ -44,7 +45,7 @@ class _CRG(Module): # Power on reset por_count = Signal(16, reset=2**16-1) por_done = Signal() - self.comb += self.cd_por.clk.eq(ClockSignal()) + self.comb += self.cd_por.clk.eq(clk100) self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) @@ -62,10 +63,11 @@ class _CRG(Module): p_DIV = "2.0", i_ALIGNWD = 0, i_CLKI = self.cd_sys2x.clk, - i_RST = self.cd_sys2x.rst, + i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n) + AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), + AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | ~rst_n | self.reset), ] # BaseSoC ------------------------------------------------------------------------------------------ @@ -87,6 +89,7 @@ class BaseSoC(SoCCore): sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) + self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy = self.ddrphy, module = MT41K256M16(sys_clk_freq, "1:2"), diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py old mode 100644 new mode 100755 index 46289ff..911c91e --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -33,13 +33,13 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) - self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True) - self.clock_domains.cd_clk10 = ClockDomain() + self.clock_domains.cd_sdcard = ClockDomain() # # # self.stop = Signal() + self.reset = Signal() # Clk / Rst clk25 = platform.request("refclk") @@ -47,7 +47,7 @@ class _CRG(Module): # Power on reset por_count = Signal(16, reset=2**16-1) por_done = Signal() - self.comb += self.cd_por.clk.eq(ClockSignal()) + self.comb += self.cd_por.clk.eq(clk25) self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) @@ -57,7 +57,7 @@ class _CRG(Module): pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_init, 24e6) - pll.create_clkout(self.cd_clk10, 10e6) + pll.create_clkout(self.cd_sdcard, 10e6) self.specials += [ Instance("ECLKBRIDGECS", i_CLK0 = self.cd_sys2x_i.clk, @@ -71,11 +71,12 @@ class _CRG(Module): p_DIV = "2.0", i_ALIGNWD = 0, i_CLKI = self.cd_sys2x.clk, - i_RST = self.cd_sys2x.rst, + i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked), - AsyncResetSynchronizer(self.cd_clk10, ~por_done | ~pll.locked) + AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked), + AsyncResetSynchronizer(self.cd_sdcard, ~por_done | ~pll.locked), + AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | self.reset), ] # USB PLL @@ -122,6 +123,7 @@ class BaseSoC(SoCCore): sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) + self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy = self.ddrphy, module = sdram_module(sys_clk_freq, "1:2"), @@ -163,14 +165,13 @@ def main(): parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") parser.add_argument("--with-sdcard", action="store_true", help="enable SDCard support") args = parser.parse_args() - + soc = BaseSoC( - toolchain = args.toolchain, - revision = args.revision, - device = args.device, - sdram_device = args.sdram_device, - with_ethernet=args.with_ethernet, - sys_clk_freq = int(float(args.sys_clk_freq)), + toolchain = args.toolchain, + device = args.device, + sdram_device = args.sdram_device, + with_ethernet = args.with_ethernet, + sys_clk_freq = int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) if args.with_sdcard: soc.add_sdcard() diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index cf759c0..d0099f6 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -37,7 +37,8 @@ class _CRG(Module): # # # - self.stop = Signal() + self.stop = Signal() + self.reset = Signal() # Clk / Rst clk48 = platform.request("clk48") @@ -45,7 +46,7 @@ class _CRG(Module): # Power on reset por_count = Signal(16, reset=2**16-1) por_done = Signal() - self.comb += self.cd_por.clk.eq(ClockSignal()) + self.comb += self.cd_por.clk.eq(clk48) self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) @@ -68,10 +69,11 @@ class _CRG(Module): p_DIV = "2.0", i_ALIGNWD = 0, i_CLKI = self.cd_sys2x.clk, - i_RST = self.cd_sys2x.rst, + i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked) + AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked), + AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | self.reset), ] # USB PLL @@ -121,6 +123,7 @@ class BaseSoC(SoCCore): sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) + self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy = self.ddrphy, module = sdram_module(sys_clk_freq, "1:2"), diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index a839a75..d14336b 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -37,7 +37,8 @@ class _CRG(Module): # # # - self.stop = Signal() + self.stop = Signal() + self.reset = Signal() # Clk / Rst clk12 = platform.request("clk12") @@ -46,7 +47,7 @@ class _CRG(Module): # Power on reset por_count = Signal(16, reset=2**16-1) por_done = Signal() - self.comb += self.cd_por.clk.eq(ClockSignal()) + self.comb += self.cd_por.clk.eq(clk12) self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) @@ -71,11 +72,12 @@ class _CRG(Module): p_DIV = "2.0", i_ALIGNWD = 0, i_CLKI = self.cd_sys2x.clk, - i_RST = self.cd_sys2x.rst, + i_RST = self.reset, o_CDIVX = self.cd_sys.clk), AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | rst), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst), - AsyncResetSynchronizer(self.cd_sdcard, ~por_done | ~pll.locked | rst) + AsyncResetSynchronizer(self.cd_sdcard, ~por_done | ~pll.locked | rst), + AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | rst | self.reset), ] self.comb += platform.request("dram_vtt_en").eq(1) @@ -97,6 +99,8 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) + self.comb += self.crg.stop.eq(self.ddrphy.init.stop) + self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index d636d7e..7bbd7ad 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -37,7 +37,8 @@ class _CRG(Module): # # # - self.stop = Signal() + self.stop = Signal() + self.reset = Signal() # Clk / Rst clk100 = platform.request("clk100") @@ -46,7 +47,7 @@ class _CRG(Module): # Power on reset por_count = Signal(16, reset=2**16-1) por_done = Signal() - self.comb += self.cd_por.clk.eq(ClockSignal()) + self.comb += self.cd_por.clk.eq(clk100) self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) @@ -64,10 +65,11 @@ class _CRG(Module): p_DIV = "2.0", i_ALIGNWD = 0, i_CLKI = self.cd_sys2x.clk, - i_RST = self.cd_sys2x.rst, + i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), - AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n) + AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n), + AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n | self.reset), + AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | ~rst_n | self.reset), ] # BaseSoC ------------------------------------------------------------------------------------------ @@ -93,6 +95,7 @@ class BaseSoC(SoCCore): sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) + self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy = self.ddrphy, module = MT41K64M16(sys_clk_freq, "1:2"),