From b1be5dcc239aea6ae380ccadd4d933063cc67208 Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Fri, 12 Jun 2020 12:04:49 -0500 Subject: [PATCH 1/2] Fix FTBFS from undersized BIOS ROM region with Microwatt Signed-off-by: Timothy Pearson --- litex_boards/targets/versa_ecp5.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 5e0e2be..62d201b 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -76,6 +76,12 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, toolchain="trellis", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain) + # Fix ROM size for Microwatt + if with_ethernet: + kwargs["integrated_rom_size"] = 0xb000 + else: + kwargs["integrated_rom_size"] = 0x9000 + # SoCCore -----------------------------------------_---------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) From 90092164c8a6b8f259ece275f8f73e9539844f2a Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Fri, 12 Jun 2020 18:33:28 -0500 Subject: [PATCH 2/2] Add device option for ECP5 Versa board Signed-off-by: Timothy Pearson --- litex_boards/platforms/versa_ecp5.py | 4 ++-- litex_boards/targets/versa_ecp5.py | 11 ++++++----- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/litex_boards/platforms/versa_ecp5.py b/litex_boards/platforms/versa_ecp5.py index 4ea3df4..861530d 100644 --- a/litex_boards/platforms/versa_ecp5.py +++ b/litex_boards/platforms/versa_ecp5.py @@ -221,8 +221,8 @@ class Platform(LatticePlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self, **kwargs): - LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs) + def __init__(self, device="LFE5UM5G-45F-8BG381C", **kwargs): + LatticePlatform.__init__(self, device, _io, _connectors, **kwargs) def create_programmer(self): return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg") diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 62d201b..c59281b 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -73,8 +73,8 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, toolchain="trellis", **kwargs): - platform = versa_ecp5.Platform(toolchain=toolchain) + def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G-45F-8BG381C", with_ethernet=False, toolchain="trellis", **kwargs): + platform = versa_ecp5.Platform(toolchain=toolchain, device=device) # Fix ROM size for Microwatt if with_ethernet: @@ -129,11 +129,12 @@ def main(): builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") + parser.add_argument("--device", default="LFE5UM5G-45F-8BG381C", help="ECP5 device (default=LFE5UM5G-45F-8BG381C)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() - soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args)) + soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), device=args.device, with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs, run=args.build)