From 159386e3d372365018ce04d070a5b6dc8f36fefc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 21 Mar 2020 20:00:56 +0100 Subject: [PATCH] targets: always use sys_clk_freq on SDRAM modules. --- litex_boards/targets/c10lprefkit.py | 2 +- litex_boards/targets/de0nano.py | 2 +- litex_boards/targets/de10lite.py | 2 +- litex_boards/targets/de1soc.py | 2 +- litex_boards/targets/genesys2.py | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 29bb1c2..e02f6e4 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -107,7 +107,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, - module = MT48LC16M16(self.clk_freq, "1:1"), + module = MT48LC16M16(sys_clk_freq, "1:1"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index d6d059f..e3ca868 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -87,7 +87,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, - module = IS42S16160(self.clk_freq, "1:1"), + module = IS42S16160(sys_clk_freq, "1:1"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index 862a2c2..d7dbbe3 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -95,7 +95,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, - module = IS42S16320(self.clk_freq, "1:1"), + module = IS42S16320(sys_clk_freq, "1:1"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py index d230c3a..61bdc52 100755 --- a/litex_boards/targets/de1soc.py +++ b/litex_boards/targets/de1soc.py @@ -87,7 +87,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, - module = IS42S16320(self.clk_freq, "1:1"), + module = IS42S16320(sys_clk_freq, "1:1"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192), diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index 3dd903e..4935382 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -59,7 +59,7 @@ class BaseSoC(SoCCore): self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, - module = MT41J256M16(self.clk_freq, "1:4"), + module = MT41J256M16(sys_clk_freq, "1:4"), origin = self.mem_map["main_ram"], size = kwargs.get("max_sdram_size", 0x40000000), l2_cache_size = kwargs.get("l2_size", 8192),