From 15a27d40fa93455b95fd03faa951c6f4842a00fa Mon Sep 17 00:00:00 2001 From: David Sawatzke Date: Thu, 9 Apr 2020 05:08:23 +0200 Subject: [PATCH] targets/colorlight_5a_75b: Change baudrate to work on v6.1 There seems to be some capacitance on KEY+, so the usual 115200 don't work --- litex_boards/targets/colorlight_5a_75b.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py index e5b4602..131213c 100755 --- a/litex_boards/targets/colorlight_5a_75b.py +++ b/litex_boards/targets/colorlight_5a_75b.py @@ -7,7 +7,7 @@ # # 1) SoC with regular UART and optional Ethernet connected to the CPU: # Connect a USB/UART to J19: TX of the FPGA is DATA_LED-, RX of the FPGA is KEY+. -# ./colorlight_5a_75b.py (add --with-ethernet to add Ethernet capability) +# ./colorlight_5a_75b.py --uart-baudrate 9600 (add --with-ethernet to add Ethernet capability) # ./colorlight_5a_75b.py --load # You should see the LiteX BIOS and be able to interact with it. #