diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py
index 80678f2..cd8e0ca 100755
--- a/litex_boards/targets/1bitsquared_icebreaker.py
+++ b/litex_boards/targets/1bitsquared_icebreaker.py
@@ -95,7 +95,6 @@ class BaseSoC(SoCCore):
         self.submodules.spram = Up5kSPRAM(size=128*kB)
         self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
 
-
         # SPI Flash --------------------------------------------------------------------------------
         from litespi.modules import W25Q128JV
         from litespi.opcodes import SpiNorFlashOpCodes as Codes
diff --git a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
index bf46cf3..3c0a885 100755
--- a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
+++ b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
@@ -91,7 +91,10 @@ class BaseSoC(SoCCore):
         self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=128*kB))
 
         # SPI Flash --------------------------------------------------------------------------------
-        self.add_spi_flash(mode="1x", dummy_cycles=8)
+        from litespi.modules import W25Q128JV
+        from litespi.opcodes import SpiNorFlashOpCodes as Codes
+        self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=False)
+        #self.add_spi_flash(mode="1x", dummy_cycles=8) # LiteX SPI Flash Core.
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(