From 16171282c8bd430c47c864bb488eb9260c1e4997 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 7 Jan 2022 14:11:52 +0100 Subject: [PATCH] digilent_arty/CRG: Add with_rst parameter to be able to easily disable rst. On Arty, cpu_rst pin is connected to a button but also to USB-UART which also resets the SoC when USB-UART is connected which is in some case not wanted. with_rst provides an easy way to disable rst by setting it to False. --- litex_boards/targets/digilent_arty.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index 50cd505..6526399 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -30,7 +30,7 @@ from liteeth.phy.mii import LiteEthPHYMII # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform, sys_clk_freq): + def __init__(self, platform, sys_clk_freq, with_rst=True): self.rst = Signal() self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) @@ -40,9 +40,12 @@ class _CRG(Module): # # # + clk100 = platform.request("clk100") + rst = ~platform.request("cpu_reset") if with_rst else 0 + self.submodules.pll = pll = S7PLL(speedgrade=-1) - self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst) - pll.register_clkin(platform.request("clk100"), 100e6) + self.comb += pll.reset.eq(rst | self.rst) + pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)