diff --git a/litex_boards/targets/stlv7325.py b/litex_boards/targets/stlv7325.py
index 1fbd7d2..934a9f3 100755
--- a/litex_boards/targets/stlv7325.py
+++ b/litex_boards/targets/stlv7325.py
@@ -59,7 +59,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6),
+    def __init__(self, sys_clk_freq=int(100e6),
         with_ethernet   = False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
         with_led_chaser = True,
         with_pcie       = False,
@@ -144,7 +144,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on STLV7325")
     parser.add_argument("--build",         action="store_true", help="Build bitstream.")
     parser.add_argument("--load",          action="store_true", help="Load bitstream.")
-    parser.add_argument("--sys-clk-freq",  default=125e6,       help="System clock frequency.")
+    parser.add_argument("--sys-clk-freq",  default=100e6,       help="System clock frequency.")
     ethopts = parser.add_mutually_exclusive_group()
     ethopts.add_argument("--with-ethernet",  action="store_true",              help="Enable Ethernet support.")
     ethopts.add_argument("--with-etherbone", action="store_true",              help="Enable Etherbone support.")