From 1631b071c3bd212919ab76306dfb5b4da8651775 Mon Sep 17 00:00:00 2001
From: Paul Sajna <sajattack@gmail.com>
Date: Thu, 30 Jan 2020 03:41:44 -0800
Subject: [PATCH] finish up sdram, passes memtest

---
 litex_boards/community/platforms/de10nano.py | 8 +++-----
 litex_boards/community/targets/de10nano.py   | 5 +----
 2 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/litex_boards/community/platforms/de10nano.py b/litex_boards/community/platforms/de10nano.py
index 162bae0..36c03ba 100644
--- a/litex_boards/community/platforms/de10nano.py
+++ b/litex_boards/community/platforms/de10nano.py
@@ -95,13 +95,11 @@ _mister_sdram_module_io = [
             "E8 V12 D11 W12 AH13 D8 AH14 AF7 AE24 AD23 AE6 AE23 AG14 AD5 AF4 AH3")),
         Subsignal("ba", Pins(
             "Y17 AB25")),
-        Subsignal("dqmh", Pins("AF13")),
-        Subsignal("dqml", Pins("AG13")),
         Subsignal("cas_n", Pins("AA18")),
         Subsignal("cs_n", Pins("Y18")),
         Subsignal("ras_n", Pins("W14")),
         Subsignal("we_n", Pins("AA19")),
-        IOStandard("3.3-V LVTTL"), Misc("SLEWRATE=FAST")
+        IOStandard("3.3-V LVTTL")
     ),
 ]
 
@@ -112,8 +110,8 @@ class Platform(AlteraPlatform):
     default_clk_period = 1e9/50e6
 
     def __init__(self):
-        # TODO uncancerify
-        AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io+_mister_sdram_module_io)
+        AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io)
+        self.add_extension(_mister_sdram_module_io)
 
     def create_programmer(self):
         return USBBlaster()
diff --git a/litex_boards/community/targets/de10nano.py b/litex_boards/community/targets/de10nano.py
index bdae67b..d8148cd 100755
--- a/litex_boards/community/targets/de10nano.py
+++ b/litex_boards/community/targets/de10nano.py
@@ -66,6 +66,7 @@ class _CRG(Module):
             AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked)
         ]
 
+        self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
@@ -94,7 +95,6 @@ class SDRAMSoC(SoCSDRAM):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform)
 
-
         # SDR SDRAM --------------------------------------------------------------------------------
 
         self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
@@ -110,8 +110,6 @@ def main():
     parser.add_argument("--with-sdram", action="store_true",
                         help="enable MiSTer SDRAM expansion board")
     builder_args(parser)
-    #soc_core_args(parser) # TODO figure out how to get args for both
-                           # core and sdram SoCs without breaking shit
     soc_sdram_args(parser)
     args = parser.parse_args()
     soc = None
@@ -119,7 +117,6 @@ def main():
         soc = SDRAMSoC(**soc_sdram_argdict(args)) 
     else:
         soc = BaseSoC(**soc_sdram_argdict(args)) 
-
     builder = Builder(soc, **builder_argdict(args))
     builder.build()