From 1655cbf62f5a1e498910bc1a36c767e3284af94c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 26 Mar 2024 14:12:07 +0100 Subject: [PATCH] alinx_axau15: Add manual loc constraints on PCIe GTHE4 channels to avoid Vivado to remap them. Board now correctly seen with lspci. --- litex_boards/targets/alinx_axau15.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/litex_boards/targets/alinx_axau15.py b/litex_boards/targets/alinx_axau15.py index f3e8638..a3cc43a 100755 --- a/litex_boards/targets/alinx_axau15.py +++ b/litex_boards/targets/alinx_axau15.py @@ -93,6 +93,13 @@ class BaseSoC(SoCCore): bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) + # Set manual locations to avoid Vivado to remap lanes to X0Y4, X0Y5, X0Y6, X0Y7. + platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~*pcie_usp_i/*GTHE4_CHANNEL_PRIM_INST}}]") + platform.toolchain.pre_placement_commands.append("set_property LOC GTHE4_CHANNEL_X0Y0 [get_cells -hierarchical -filter {{NAME=~*pcie_usp_i/*gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}}]") + platform.toolchain.pre_placement_commands.append("set_property LOC GTHE4_CHANNEL_X0Y1 [get_cells -hierarchical -filter {{NAME=~*pcie_usp_i/*gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}}]") + platform.toolchain.pre_placement_commands.append("set_property LOC GTHE4_CHANNEL_X0Y2 [get_cells -hierarchical -filter {{NAME=~*pcie_usp_i/*gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}}]") + platform.toolchain.pre_placement_commands.append("set_property LOC GTHE4_CHANNEL_X0Y3 [get_cells -hierarchical -filter {{NAME=~*pcie_usp_i/*gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}}]") + # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.ethphy = LiteEthPHYRGMII(