diff --git a/litex_boards/platforms/sitlinv_stlv7325.py b/litex_boards/platforms/sitlinv_stlv7325.py index ec7a4a5..2bf0026 100644 --- a/litex_boards/platforms/sitlinv_stlv7325.py +++ b/litex_boards/platforms/sitlinv_stlv7325.py @@ -144,14 +144,14 @@ _io = [ # GMII Ethernet ("eth_clocks", 0, - Subsignal("tx", Pins("E12"), IOStandard("LVCMOS15")), - Subsignal("gtx", Pins("F13"), IOStandard("LVCMOS15")), - Subsignal("rx", Pins("C12"), IOStandard("LVCMOS15")) + Subsignal("tx", Pins("E12"), IOStandard("LVCMOS25")), + Subsignal("gtx", Pins("F13"), IOStandard("LVCMOS25")), + Subsignal("rx", Pins("C12"), IOStandard("LVCMOS25")) ), ("eth_clocks", 1, - Subsignal("tx", Pins("C9"), IOStandard("LVCMOS15")), - Subsignal("gtx", Pins("D8"), IOStandard("LVCMOS15")), - Subsignal("rx", Pins("E10"), IOStandard("LVCMOS15")) + Subsignal("tx", Pins("C9"), IOStandard("LVCMOS25")), + Subsignal("gtx", Pins("D8"), IOStandard("LVCMOS25")), + Subsignal("rx", Pins("E10"), IOStandard("LVCMOS25")) ), ("eth", 0, Subsignal("rst_n", Pins("D11")), @@ -164,9 +164,7 @@ _io = [ Subsignal("tx_en", Pins("F12")), Subsignal("tx_er", Pins("E13")), Subsignal("tx_data", Pins("G12 E11 G11 C14 D14 C13 C11 D13")), - Subsignal("col", Pins("W19")), - Subsignal("crs", Pins("R30")), - IOStandard("LVCMOS15") + IOStandard("LVCMOS25") ), ("eth", 1, Subsignal("rst_n", Pins("J8")), @@ -179,9 +177,7 @@ _io = [ Subsignal("tx_en", Pins("F8")), Subsignal("tx_er", Pins("D9")), Subsignal("tx_data", Pins("H11 J11 H9 J10 H12 F10 G10 F9")), - Subsignal("col", Pins("W19")), - Subsignal("crs", Pins("R30")), - IOStandard("LVCMOS15") + IOStandard("LVCMOS25") ), # HDMI out diff --git a/litex_boards/targets/sitlinv_stlv7325.py b/litex_boards/targets/sitlinv_stlv7325.py index ff58142..83ff03b 100755 --- a/litex_boards/targets/sitlinv_stlv7325.py +++ b/litex_boards/targets/sitlinv_stlv7325.py @@ -63,11 +63,13 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=100e6, with_ethernet = False, with_etherbone = False, - eth_ip = "192.168.1.50", + local_ip = "192.168.1.50", + remote_ip = "", eth_dynamic_ip = False, with_led_chaser = True, with_pcie = False, with_sata = False, + with_jtagbone = True, **kwargs): platform = sitlinv_stlv7325.Platform() @@ -75,7 +77,7 @@ class BaseSoC(SoCCore): self.crg = _CRG(platform, sys_clk_freq) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on AliExpress STLV7325", **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Sitlinv STLV7325", **kwargs) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: @@ -90,6 +92,10 @@ class BaseSoC(SoCCore): l2_cache_size = kwargs.get("l2_size", 8192), ) + # Jtagbone --------------------------------------------------------------------------------- + if with_jtagbone: + self.add_jtagbone() + # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.ethphy = LiteEthPHY( @@ -97,10 +103,24 @@ class BaseSoC(SoCCore): pads = self.platform.request("eth", 0), clk_freq = self.clk_freq) if with_ethernet: - self.add_ethernet(phy=self.ethphy) + self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy) + if local_ip: + local_ip = local_ip.split(".") + self.add_constant("LOCALIP1", int(local_ip[0])) + self.add_constant("LOCALIP2", int(local_ip[1])) + self.add_constant("LOCALIP3", int(local_ip[2])) + self.add_constant("LOCALIP4", int(local_ip[3])) + + if remote_ip: + remote_ip = remote_ip.split(".") + self.add_constant("REMOTEIP1", int(remote_ip[0])) + self.add_constant("REMOTEIP2", int(remote_ip[1])) + self.add_constant("REMOTEIP3", int(remote_ip[2])) + self.add_constant("REMOTEIP4", int(remote_ip[3])) + # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), @@ -149,24 +169,30 @@ def main(): ethopts = parser.target_group.add_mutually_exclusive_group() ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") - parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.") + parser.add_target_argument("--remote-ip", default="192.168.1.100",help="Remote IP address of TFTP server.") + parser.add_target_argument("--local-ip", default="192.168.1.50", help="Local IP address.") parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.") parser.add_target_argument("--with-sata", action="store_true", help="Enable SATA support.") + parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.") sdopts = parser.target_group.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") args = parser.parse_args() + assert not (args.with_etherbone and args.eth_dynamic_ip) + soc = BaseSoC( sys_clk_freq = args.sys_clk_freq, with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, - eth_ip = args.eth_ip, + local_ip = args.local_ip, + remote_ip = args.remote_ip, eth_dynamic_ip = args.eth_dynamic_ip, with_pcie = args.with_pcie, with_sata = args.with_sata, + with_jtagbone = args.with_jtagbone, **parser.soc_argdict ) if args.with_spi_sdcard: