From 1c07fa94ca55ff48b3d6e803c21934db08f75571 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 4 Nov 2022 10:51:47 +0800 Subject: [PATCH 1/6] sitlinv_stlv7325: fix ident string vendor name As we changed the vendor name to proper Sitlinv in the file name, the ident string is left untouched. Fix this too. Signed-off-by: Icenowy Zheng --- litex_boards/targets/sitlinv_stlv7325.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/sitlinv_stlv7325.py b/litex_boards/targets/sitlinv_stlv7325.py index ff58142..ce58825 100755 --- a/litex_boards/targets/sitlinv_stlv7325.py +++ b/litex_boards/targets/sitlinv_stlv7325.py @@ -75,7 +75,7 @@ class BaseSoC(SoCCore): self.crg = _CRG(platform, sys_clk_freq) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on AliExpress STLV7325", **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Sitlinv STLV7325", **kwargs) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: From 4ba57938222bbcfebea612862c9ccb349c82051e Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 4 Nov 2022 10:52:33 +0800 Subject: [PATCH 2/6] sitlinv_stlv7325: remove unexistent COL/CRS pins The COL and CRS pins of the Ethernet PHY is not connected on the board at all, but assigned dummy positions in the platform definition, which leads to Vivado warning when building. Remove these pins from the platform definition. Signed-off-by: Icenowy Zheng --- litex_boards/platforms/sitlinv_stlv7325.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/litex_boards/platforms/sitlinv_stlv7325.py b/litex_boards/platforms/sitlinv_stlv7325.py index ec7a4a5..992ba64 100644 --- a/litex_boards/platforms/sitlinv_stlv7325.py +++ b/litex_boards/platforms/sitlinv_stlv7325.py @@ -164,8 +164,6 @@ _io = [ Subsignal("tx_en", Pins("F12")), Subsignal("tx_er", Pins("E13")), Subsignal("tx_data", Pins("G12 E11 G11 C14 D14 C13 C11 D13")), - Subsignal("col", Pins("W19")), - Subsignal("crs", Pins("R30")), IOStandard("LVCMOS15") ), ("eth", 1, @@ -179,8 +177,6 @@ _io = [ Subsignal("tx_en", Pins("F8")), Subsignal("tx_er", Pins("D9")), Subsignal("tx_data", Pins("H11 J11 H9 J10 H12 F10 G10 F9")), - Subsignal("col", Pins("W19")), - Subsignal("crs", Pins("R30")), IOStandard("LVCMOS15") ), From 27c3afb8fbccc23af52c6b66f748c0f5393acabe Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 4 Nov 2022 10:53:35 +0800 Subject: [PATCH 3/6] sitlinv_stlv7325: allow dynamic Ethernet IP Currently the sitlinv_stlv7325 target script parses the option that selects dynamic Ethernet IP; however it's not really passed to LiteETH. Really pass this option and add an assert that does not allow dynamic Etherbone IP like other boards. Signed-off-by: Icenowy Zheng --- litex_boards/targets/sitlinv_stlv7325.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litex_boards/targets/sitlinv_stlv7325.py b/litex_boards/targets/sitlinv_stlv7325.py index ce58825..bfe051f 100755 --- a/litex_boards/targets/sitlinv_stlv7325.py +++ b/litex_boards/targets/sitlinv_stlv7325.py @@ -97,7 +97,7 @@ class BaseSoC(SoCCore): pads = self.platform.request("eth", 0), clk_freq = self.clk_freq) if with_ethernet: - self.add_ethernet(phy=self.ethphy) + self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) if with_etherbone: self.add_etherbone(phy=self.ethphy) @@ -159,6 +159,8 @@ def main(): sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") args = parser.parse_args() + assert not (args.with_etherbone and args.eth_dynamic_ip) + soc = BaseSoC( sys_clk_freq = args.sys_clk_freq, with_ethernet = args.with_ethernet, From 3d8106f84d6f41964506a9395a9fb70db9c3d87d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 8 Nov 2022 19:18:24 +0800 Subject: [PATCH 4/6] stlv7325: fix Ethernet IO voltages The IO voltages of Ethernet pins is set to 2.5V instead of 1.5V. Fix this in the platform definition. Signed-off-by: Icenowy Zheng --- litex_boards/platforms/sitlinv_stlv7325.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/litex_boards/platforms/sitlinv_stlv7325.py b/litex_boards/platforms/sitlinv_stlv7325.py index 992ba64..2bf0026 100644 --- a/litex_boards/platforms/sitlinv_stlv7325.py +++ b/litex_boards/platforms/sitlinv_stlv7325.py @@ -144,14 +144,14 @@ _io = [ # GMII Ethernet ("eth_clocks", 0, - Subsignal("tx", Pins("E12"), IOStandard("LVCMOS15")), - Subsignal("gtx", Pins("F13"), IOStandard("LVCMOS15")), - Subsignal("rx", Pins("C12"), IOStandard("LVCMOS15")) + Subsignal("tx", Pins("E12"), IOStandard("LVCMOS25")), + Subsignal("gtx", Pins("F13"), IOStandard("LVCMOS25")), + Subsignal("rx", Pins("C12"), IOStandard("LVCMOS25")) ), ("eth_clocks", 1, - Subsignal("tx", Pins("C9"), IOStandard("LVCMOS15")), - Subsignal("gtx", Pins("D8"), IOStandard("LVCMOS15")), - Subsignal("rx", Pins("E10"), IOStandard("LVCMOS15")) + Subsignal("tx", Pins("C9"), IOStandard("LVCMOS25")), + Subsignal("gtx", Pins("D8"), IOStandard("LVCMOS25")), + Subsignal("rx", Pins("E10"), IOStandard("LVCMOS25")) ), ("eth", 0, Subsignal("rst_n", Pins("D11")), @@ -164,7 +164,7 @@ _io = [ Subsignal("tx_en", Pins("F12")), Subsignal("tx_er", Pins("E13")), Subsignal("tx_data", Pins("G12 E11 G11 C14 D14 C13 C11 D13")), - IOStandard("LVCMOS15") + IOStandard("LVCMOS25") ), ("eth", 1, Subsignal("rst_n", Pins("J8")), @@ -177,7 +177,7 @@ _io = [ Subsignal("tx_en", Pins("F8")), Subsignal("tx_er", Pins("D9")), Subsignal("tx_data", Pins("H11 J11 H9 J10 H12 F10 G10 F9")), - IOStandard("LVCMOS15") + IOStandard("LVCMOS25") ), # HDMI out From c2c59f5e8c0941e05a30904f2ce5bc151290dda9 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 13 Nov 2022 17:27:58 +0800 Subject: [PATCH 5/6] sitlinv_stlv7325: allow to set local/remote ip Port the script snippet from Colorlight i5 for setting the local/remote IP address to STLV7325. Signed-off-by: Icenowy Zheng --- litex_boards/targets/sitlinv_stlv7325.py | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/sitlinv_stlv7325.py b/litex_boards/targets/sitlinv_stlv7325.py index bfe051f..6ba84ad 100755 --- a/litex_boards/targets/sitlinv_stlv7325.py +++ b/litex_boards/targets/sitlinv_stlv7325.py @@ -63,7 +63,8 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=100e6, with_ethernet = False, with_etherbone = False, - eth_ip = "192.168.1.50", + local_ip = "192.168.1.50", + remote_ip = "", eth_dynamic_ip = False, with_led_chaser = True, with_pcie = False, @@ -101,6 +102,20 @@ class BaseSoC(SoCCore): if with_etherbone: self.add_etherbone(phy=self.ethphy) + if local_ip: + local_ip = local_ip.split(".") + self.add_constant("LOCALIP1", int(local_ip[0])) + self.add_constant("LOCALIP2", int(local_ip[1])) + self.add_constant("LOCALIP3", int(local_ip[2])) + self.add_constant("LOCALIP4", int(local_ip[3])) + + if remote_ip: + remote_ip = remote_ip.split(".") + self.add_constant("REMOTEIP1", int(remote_ip[0])) + self.add_constant("REMOTEIP2", int(remote_ip[1])) + self.add_constant("REMOTEIP3", int(remote_ip[2])) + self.add_constant("REMOTEIP4", int(remote_ip[3])) + # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), @@ -149,7 +164,8 @@ def main(): ethopts = parser.target_group.add_mutually_exclusive_group() ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") - parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.") + parser.add_target_argument("--remote-ip", default="192.168.1.100",help="Remote IP address of TFTP server.") + parser.add_target_argument("--local-ip", default="192.168.1.50", help="Local IP address.") parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.") @@ -165,7 +181,8 @@ def main(): sys_clk_freq = args.sys_clk_freq, with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, - eth_ip = args.eth_ip, + local_ip = args.local_ip, + remote_ip = args.remote_ip, eth_dynamic_ip = args.eth_dynamic_ip, with_pcie = args.with_pcie, with_sata = args.with_sata, From e9d7013d707eacf7acaac640de3b3452e7653771 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 13 Nov 2022 17:23:48 +0800 Subject: [PATCH 6/6] sitlinv_stlv7325: add jtagbone support Add necessary script snippets for enabling jtagbone in the command line. Signed-off-by: Icenowy Zheng --- litex_boards/targets/sitlinv_stlv7325.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/litex_boards/targets/sitlinv_stlv7325.py b/litex_boards/targets/sitlinv_stlv7325.py index 6ba84ad..83ff03b 100755 --- a/litex_boards/targets/sitlinv_stlv7325.py +++ b/litex_boards/targets/sitlinv_stlv7325.py @@ -69,6 +69,7 @@ class BaseSoC(SoCCore): with_led_chaser = True, with_pcie = False, with_sata = False, + with_jtagbone = True, **kwargs): platform = sitlinv_stlv7325.Platform() @@ -91,6 +92,10 @@ class BaseSoC(SoCCore): l2_cache_size = kwargs.get("l2_size", 8192), ) + # Jtagbone --------------------------------------------------------------------------------- + if with_jtagbone: + self.add_jtagbone() + # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.ethphy = LiteEthPHY( @@ -170,6 +175,7 @@ def main(): parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") parser.add_target_argument("--driver", action="store_true", help="Generate PCIe driver.") parser.add_target_argument("--with-sata", action="store_true", help="Enable SATA support.") + parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.") sdopts = parser.target_group.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") @@ -186,6 +192,7 @@ def main(): eth_dynamic_ip = args.eth_dynamic_ip, with_pcie = args.with_pcie, with_sata = args.with_sata, + with_jtagbone = args.with_jtagbone, **parser.soc_argdict ) if args.with_spi_sdcard: