From 1717af68acbd832dc3b86466f67a7d0c1d1ef8bc Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 23 Feb 2022 10:38:01 +0100
Subject: [PATCH] targets/sqrl_acorn/ddr3: Disable write_latency_calibration.

Introduce some memtest failures on some boards.
---
 litex_boards/targets/sqrl_acorn.py | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/litex_boards/targets/sqrl_acorn.py b/litex_boards/targets/sqrl_acorn.py
index fdb01e3..352db78 100755
--- a/litex_boards/targets/sqrl_acorn.py
+++ b/litex_boards/targets/sqrl_acorn.py
@@ -87,10 +87,11 @@ class BaseSoC(SoCCore):
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
-                memtype          = "DDR3",
-                nphases          = 4,
-                sys_clk_freq     = sys_clk_freq,
-                iodelay_clk_freq = 200e6)
+                memtype                   = "DDR3",
+                nphases                   = 4,
+                sys_clk_freq              = sys_clk_freq,
+                iodelay_clk_freq          = 200e6,
+                write_latency_calibration = False)
             self.add_sdram("sdram",
                 phy           = self.ddrphy,
                 module        = MT41K512M16(sys_clk_freq, "1:4"),