From 174d958ca767c5604b4d253d7a5b3a3e04074299 Mon Sep 17 00:00:00 2001 From: Andrew Gillham Date: Wed, 2 Feb 2022 11:16:48 -0600 Subject: [PATCH] Initial support for STLV7325 Kintex-7 board. --- litex_boards/platforms/stlv7325.py | 315 +++++++++++++++++++++++++++++ litex_boards/targets/stlv7325.py | 163 +++++++++++++++ 2 files changed, 478 insertions(+) create mode 100644 litex_boards/platforms/stlv7325.py create mode 100755 litex_boards/targets/stlv7325.py diff --git a/litex_boards/platforms/stlv7325.py b/litex_boards/platforms/stlv7325.py new file mode 100644 index 0000000..6d6a866 --- /dev/null +++ b/litex_boards/platforms/stlv7325.py @@ -0,0 +1,315 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2022 Andrew Gillham +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform +from litex.build.openocd import OpenOCD + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk / Rst + ("clk200", 0, + Subsignal("p", Pins("AB11"), IOStandard("DIFF_SSTL15")), + Subsignal("n", Pins("AC11"), IOStandard("DIFF_SSTL15")) + ), + # TODO verify / test (in docs) + ("clk156", 0, + Subsignal("p", Pins("D6"), IOStandard("LVDS")), + Subsignal("n", Pins("D5"), IOStandard("LVDS")), + ), + # TODO verify / test (in docs) + ("clk150", 0, + Subsignal("p", Pins("F6"), IOStandard("LVDS")), + Subsignal("n", Pins("F5"), IOStandard("LVDS")), + ), + ("clk100", 0, Pins("F17"), IOStandard("LVCMOS25")), + + # active low + ("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")), + + # active low + ("user_led_n", 0, Pins("AA2"), IOStandard("LVCMOS15")), + ("user_led_n", 1, Pins("AD5"), IOStandard("LVCMOS15")), + ("user_led_n", 2, Pins("W10"), IOStandard("LVCMOS15")), + ("user_led_n", 3, Pins("Y10"), IOStandard("LVCMOS15")), + ("user_led_n", 4, Pins("AE10"), IOStandard("LVCMOS15")), + ("user_led_n", 5, Pins("W11"), IOStandard("LVCMOS15")), + ("user_led_n", 6, Pins("V11"), IOStandard("LVCMOS15")), + ("user_led_n", 7, Pins("Y12"), IOStandard("LVCMOS15")), + + # active low + ("user_key2_n", 0, Pins("AC16"), IOStandard("LVCMOS15")), + ("user_key3_n", 0, Pins("C24"), IOStandard("LVCMOS33")), # J4 jumper 2.5V or 3.3V + + # I2C + ("i2c", 0, # AT24C04 + Subsignal("scl", Pins("U19")), + Subsignal("sda", Pins("U20")), + IOStandard("LVCMOS25")), + + # Serial + ("serial", 0, + Subsignal("tx", Pins("M25")), # CH340_TX + Subsignal("rx", Pins("L25")), # CH340_RX + IOStandard("LVCMOS25") + ), + + # DDR3 SDRAM + ("ddram", 0, + Subsignal("a", Pins( + "AB7 AD11 AA8 AF10 AC7 AE11 AC8 AD8", + "AC13 AF12 AF9 AD10 AE13 AF7 AB12"), + IOStandard("SSTL15")), + Subsignal("ba", Pins("AE8 AA7 AF13"), IOStandard("SSTL15")), + Subsignal("ras_n", Pins("Y7"), IOStandard("SSTL15")), + Subsignal("cas_n", Pins("AE7"), IOStandard("SSTL15")), + Subsignal("we_n", Pins("AF8"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("AA13"), IOStandard("SSTL15")), # 1R + # Subsignal("cs_n", Pins("AD13"), IOStandard("SSTL15")), # 2R + Subsignal("dm", Pins( + "AD16 AB16 AB19 V17 U1 AA3 AD6 AE1"), + IOStandard("SSTL15")), + Subsignal("dq", Pins( + "AF17 AE17 AF15 AF14 AE15 AD15 AF20 AF19", + "AA15 AA14 AC14 AD14 AB14 AB15 AA18 AA17", + "AC18 AD18 AC17 AB17 AA20 AA19 AD19 AC19", + "W14 V14 V19 V18 V16 W15 W16 Y17", + "V4 U6 U5 U2 V3 W3 U7 V6", + "Y3 Y2 V2 V1 W1 Y1 AB2 AC2", + "AA4 AB4 AC4 AC3 AC6 AB6 Y6 Y5", + "AD4 AD1 AF2 AE2 AE6 AE5 AF3 AE3"), + IOStandard("SSTL15_T_DCI")), + Subsignal("dqs_p", Pins("AE18 Y15 AD20 W18 W6 AB1 AA5 AF5"), + IOStandard("DIFF_SSTL15")), + Subsignal("dqs_n", Pins("AF18 Y16 AE20 W19 W5 AC1 AB5 AF4"), + IOStandard("DIFF_SSTL15")), + Subsignal("clk_p", Pins("AC9"), IOStandard("DIFF_SSTL15")), # 1R + Subsignal("clk_n", Pins("AD9"), IOStandard("DIFF_SSTL15")), # 1R + # Subsignal("clk_p", Pins("AA10"), IOStandard("DIFF_SSTL15")), # 2R + # Subsignal("clk_n", Pins("AB10"), IOStandard("DIFF_SSTL15")), # 2R + Subsignal("cke", Pins("AB9"), IOStandard("SSTL15")), # 1R + # Subsignal("cke", Pins("AA9"), IOStandard("SSTL15")), # 2R + Subsignal("odt", Pins("AA12"), IOStandard("SSTL15")), # 1R + # Subsignal("odt", Pins("Y13"), IOStandard("SSTL15")), # 2R + Subsignal("reset_n", Pins("AB20"), IOStandard("LVCMOS15")), + Misc("SLEW=FAST"), + Misc("VCCAUX_IO=NORMAL") + ), + + ## TODO verify / test + # # SPIFlash + # ("spiflash", 0, + # Subsignal("cs_n", Pins("C23")), + # Subsignal("clk", Pins("C8")), + # Subsignal("dq", Pins("B24 A25 B22 A22")), + # IOStandard("LVCMOS25") + # ), + + # Sata + ("sata", 0, + Subsignal("rx_p", Pins("R4")), + Subsignal("rx_n", Pins("R3")), + Subsignal("tx_p", Pins("P2")), + Subsignal("tx_n", Pins("P1")), + IOStandard("LVCMOS33"), + ), + ("sata", 1, + Subsignal("rx_p", Pins("N4")), + Subsignal("rx_n", Pins("N3")), + Subsignal("tx_p", Pins("M2")), + Subsignal("tx_n", Pins("M1")), + IOStandard("LVCMOS33"), + ), + + # SDCard + ("spisdcard", 0, + Subsignal("clk", Pins("N21")), + Subsignal("cs_n", Pins("P19")), + Subsignal("mosi", Pins("U21"), Misc("PULLUP")), + Subsignal("miso", Pins("N16"), Misc("PULLUP")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS25") + ), + ("sdcard", 0, + Subsignal("clk", Pins("N21")), + Subsignal("cmd", Pins("U21"), Misc("PULLUP True")), + Subsignal("data", Pins("N16 U16 N22 P19"), Misc("PULLUP True")), + Misc("SLEW=FAST"), + IOStandard("LVCMOS25") + ), + + # GMII Ethernet + ("eth_clocks", 0, + Subsignal("tx", Pins("E12"), IOStandard("LVCMOS15")), + Subsignal("gtx", Pins("F13"), IOStandard("LVCMOS15")), + Subsignal("rx", Pins("C12"), IOStandard("LVCMOS15")) + ), + ("eth_clocks", 1, + Subsignal("tx", Pins("C9"), IOStandard("LVCMOS15")), + Subsignal("gtx", Pins("D8"), IOStandard("LVCMOS15")), + Subsignal("rx", Pins("E10"), IOStandard("LVCMOS15")) + ), + ("eth", 0, + Subsignal("rst_n", Pins("D11")), + # Subsignal("int_n", Pins("")), + Subsignal("mdio", Pins("K15")), + Subsignal("mdc", Pins("M16")), + Subsignal("rx_dv", Pins("G14")), + Subsignal("rx_er", Pins("F14")), + Subsignal("rx_data", Pins("H14 J14 J13 H13 B15 A15 B14 A14")), + Subsignal("tx_en", Pins("F12")), + Subsignal("tx_er", Pins("E13")), + Subsignal("tx_data", Pins("G12 E11 G11 C14 D14 C13 C11 D13")), + Subsignal("col", Pins("W19")), + Subsignal("crs", Pins("R30")), + IOStandard("LVCMOS15") + ), + ("eth", 1, + Subsignal("rst_n", Pins("J8")), + # Subsignal("int_n", Pins("")), + Subsignal("mdio", Pins("G9")), + Subsignal("mdc", Pins("H8")), + Subsignal("rx_dv", Pins("A12")), + Subsignal("rx_er", Pins("D10")), + Subsignal("rx_data", Pins("A13 B12 B11 A10 B10 A9 B9 A8")), + Subsignal("tx_en", Pins("F8")), + Subsignal("tx_er", Pins("D9")), + Subsignal("tx_data", Pins("H11 J11 H9 J10 H12 F10 G10 F9")), + Subsignal("col", Pins("W19")), + Subsignal("crs", Pins("R30")), + IOStandard("LVCMOS15") + ), + + # HDMI out + ("hdmi_out", 0, + Subsignal("clk_p", Pins("R21"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("P21"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("N18"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("M19"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("M21"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("M22"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("K25"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("K26"), IOStandard("TMDS_33")), + Subsignal("scl", Pins("K21"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("L23"), IOStandard("LVCMOS33")), + Subsignal("hdp", Pins("N26"), IOStandard("LVCMOS33")), + Subsignal("cec", Pins("M26"), IOStandard("LVCMOS33")), + ), + + # PCIe + ("pcie_x1", 0, + Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")), + Subsignal("clk_p", Pins("H6")), + Subsignal("clk_n", Pins("H5")), + Subsignal("rx_p", Pins("B6")), + Subsignal("rx_n", Pins("B5")), + Subsignal("tx_p", Pins("A4")), + Subsignal("tx_n", Pins("A3")) + ), + ("pcie_x2", 0, + Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")), + Subsignal("clk_p", Pins("H6")), + Subsignal("clk_n", Pins("H5")), + Subsignal("rx_p", Pins("B6 C4")), + Subsignal("rx_n", Pins("B5 C3")), + Subsignal("tx_p", Pins("A4 B2")), + Subsignal("tx_n", Pins("A3 B1")) + ), + ("pcie_x4", 0, + Subsignal("rst_n", Pins("E17"), IOStandard("LVCMOS15")), + Subsignal("clk_p", Pins("H6")), + Subsignal("clk_n", Pins("H5")), + Subsignal("rx_p", Pins("B6 C4 E4 G4")), + Subsignal("rx_n", Pins("B5 C3 E3 G3")), + Subsignal("tx_p", Pins("A4 B2 D2 F2")), + Subsignal("tx_n", Pins("A3 B1 D1 F1")) + ), + + # TODO find / test + # # SGMII Clk + # ("sgmii_clock", 0, + # Subsignal("p", Pins("")), + # Subsignal("n", Pins("")) + # ), + + # SFP + ("sfp_a", 0, # SFP A + Subsignal("txp", Pins("H2")), + Subsignal("txn", Pins("H1")), + Subsignal("rxp", Pins("J4")), + Subsignal("rxn", Pins("J3")), + Subsignal("sda", Pins("B21")), + Subsignal("scl", Pins("C21")), + ), + ("sfp_a_tx", 0, # SFP A + Subsignal("p", Pins("H2")), + Subsignal("n", Pins("H1")) + ), + ("sfp_a_rx", 0, # SFP A + Subsignal("p", Pins("J4")), + Subsignal("n", Pins("J3")) + ), + ("sfp_b", 0, # SFP B + Subsignal("txp", Pins("K2")), + Subsignal("txn", Pins("K1")), + Subsignal("rxp", Pins("L4")), + Subsignal("rxn", Pins("L3")), + Subsignal("sda", Pins("D21")), + Subsignal("scl", Pins("C22")), + ), + ("sfp_b_tx", 0, # SFP B + Subsignal("p", Pins("K2")), + Subsignal("n", Pins("K1")) + ), + ("sfp_b_rx", 0, # SFP B + Subsignal("p", Pins("L4")), + Subsignal("n", Pins("L3")) + ), + + # SI5338 (optional part per seller?) + ("si5338_i2c", 0, + Subsignal("sck", Pins("U19"), IOStandard("LVCMOS25")), + Subsignal("sda", Pins("U20"), IOStandard("LVCMOS25")) + ), + ("si5338_clkin", 0, # CLK2A/B + Subsignal("p", Pins("K6"), IOStandard("LVDS_25")), + Subsignal("n", Pins("K5"), IOStandard("LVDS_25")) + ), +] + +# Connectors --------------------------------------------------------------------------------------- + +_connectors = [ + # TODO; add FMC / BTB +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "clk200" + default_clk_period = 1e9/200e6 + + def __init__(self): + XilinxPlatform.__init__(self, "xc7k325t-ffg676-2", _io, _connectors, toolchain="vivado") + self.add_platform_command(""" +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 2.5 [current_design] +""") + self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] + self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] + + def create_programmer(self): + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit") + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) + self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6) + self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6) + self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6) + self.add_period_constraint(self.lookup_request("eth_clocks:tx", 1, loose=True), 1e9/125e6) + self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]") diff --git a/litex_boards/targets/stlv7325.py b/litex_boards/targets/stlv7325.py new file mode 100755 index 0000000..0c6eca1 --- /dev/null +++ b/litex_boards/targets/stlv7325.py @@ -0,0 +1,163 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2022 Andrew Gillham +# Copyright (c) 2014-2015 Sebastien Bourdeauducq +# Copyright (c) 2014-2020 Florent Kermarrec +# Copyright (c) 2014-2015 Yann Sionneau +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen import * + +from litex_boards.platforms import stlv7325 + +from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser +from litex.soc.cores.bitbang import I2CMaster + +from litedram.modules import DDR3Module +from litedram.modules import MT8JTF12864 +from litedram.phy import s7ddrphy + +from liteeth.phy import LiteEthPHY + +from litepcie.phy.s7pciephy import S7PCIEPHY +from litepcie.software import generate_litepcie_software + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_idelay = ClockDomain() + + # # # + + self.submodules.pll = pll = S7MMCM(speedgrade=-2) + self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst) + pll.register_clkin(platform.request("clk200"), 200e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_idelay, 200e6) + platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_led_chaser=True, + with_pcie=False, with_sata=False, **kwargs): + platform = stlv7325.Platform() + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on STLV7325", + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # DDR3 SDRAM ------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), + memtype = "DDR3", + nphases = 4, + sys_clk_freq = sys_clk_freq) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT8JTF12864(sys_clk_freq, "1:4"), + size = 0x40000000, + l2_cache_size = kwargs.get("l2_size", 8192) + ) + + # Ethernet --------------------------------------------------------------------------------- + if with_ethernet: + self.submodules.ethphy = LiteEthPHY( + clock_pads = self.platform.request("eth_clocks", 0), + pads = self.platform.request("eth", 0), + clk_freq = self.clk_freq) + self.add_ethernet(phy=self.ethphy) + + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), + data_width = 128, + bar0_size = 0x20000) + self.add_pcie(phy=self.pcie_phy, ndmas=1) + + # TODO verify / test + # SATA ------------------------------------------------------------------------------------- + if with_sata: + from litex.build.generic_platform import Subsignal, Pins + from litesata.phy import LiteSATAPHY + + # RefClk, Generate 150MHz from PLL. + self.clock_domains.cd_sata_refclk = ClockDomain() + self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6) + sata_refclk = ClockSignal("sata_refclk") + platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]") + + # PHY + self.submodules.sata_phy = LiteSATAPHY(platform.device, + refclk = sata_refclk, + pads = platform.request("sata", 0), + gen = "gen2", + clk_freq = sys_clk_freq, + data_width = 16) + + # Core + self.add_sata(phy=self.sata_phy, mode="read+write") + + # Leds ------------------------------------------------------------------------------------- + if with_led_chaser: + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led_n"), + sys_clk_freq = sys_clk_freq) + + # I2C -------------------------------------------------------------------------------------- + self.submodules.i2c = I2CMaster(platform.request("i2c")) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on STLV7325") + parser.add_argument("--build", action="store_true", help="Build bitstream.") + parser.add_argument("--load", action="store_true", help="Load bitstream.") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.") + parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over SFP2SATA).") + builder_args(parser) + soc_core_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + with_pcie = args.with_pcie, + with_sata = args.with_sata, + **soc_core_argdict(args) + ) + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) + +if __name__ == "__main__": + main()