From 188d4a45d64f4c1ec1eb092d1911c6f092d46740 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Apr 2020 11:46:23 +0200 Subject: [PATCH] targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets. --- litex_boards/targets/colorlight_5a_75b.py | 4 +++- litex_boards/targets/de0nano.py | 4 +++- litex_boards/targets/de10lite.py | 4 +++- litex_boards/targets/de10nano.py | 6 ++++-- litex_boards/targets/de1soc.py | 4 +++- litex_boards/targets/de2_115.py | 4 +++- litex_boards/targets/hadbadge.py | 4 +++- litex_boards/targets/linsn_rv901t.py | 4 ++-- litex_boards/targets/minispartan6.py | 4 ++-- litex_boards/targets/ulx3s.py | 4 +++- 10 files changed, 29 insertions(+), 13 deletions(-) diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py index 1d77bb5..191d2dc 100755 --- a/litex_boards/targets/colorlight_5a_75b.py +++ b/litex_boards/targets/colorlight_5a_75b.py @@ -30,6 +30,8 @@ import sys from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.build.io import DDROutput + from litex_boards.platforms import colorlight_5a_75b from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -66,7 +68,7 @@ class _CRG(Module): self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n) # SDRAM clock - self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index 5001778..2f8cd47 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -8,6 +8,8 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.build.io import DDROutput + from litex_boards.platforms import de0nano from litex.soc.cores.clock import CycloneIVPLL @@ -38,7 +40,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock - self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index c1fedcd..bdcbd71 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -8,6 +8,8 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.build.io import DDROutput + from litex_boards.platforms import de10lite from litex.soc.cores.clock import Max10PLL @@ -42,7 +44,7 @@ class _CRG(Module): pll.create_clkout(self.cd_vga, 25e6) # SDRAM clock - self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index 008f28f..878228e 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -8,6 +8,8 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.build.io import DDROutput + from litex_boards.platforms import de10nano from litex.soc.cores.clock import CycloneVPLL @@ -37,9 +39,9 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) - # SDRAM + # SDRAM clock if with_sdram: - self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py index 6a5885a..8c1a375 100755 --- a/litex_boards/targets/de1soc.py +++ b/litex_boards/targets/de1soc.py @@ -8,6 +8,8 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.build.io import DDROutput + from litex_boards.platforms import de1soc from litex.soc.cores.clock import CycloneVPLL @@ -38,7 +40,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock - self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/de2_115.py b/litex_boards/targets/de2_115.py index ce32efe..a75b2ba 100755 --- a/litex_boards/targets/de2_115.py +++ b/litex_boards/targets/de2_115.py @@ -8,6 +8,8 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.build.io import DDROutput + from litex_boards.platforms import de2_115 from litex.soc.cores.clock import CycloneIVPLL @@ -38,7 +40,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock - self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index 3d4ced2..629aeb2 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -12,6 +12,8 @@ import sys from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.build.io import DDROutput + from litex_boards.platforms import hadbadge from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -46,7 +48,7 @@ class _CRG(Module): self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked) # SDRAM clock - self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index b8057c8..cc8abc0 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -40,7 +40,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # SDRAM clock - self.specials += DDROutput(0, 1, platform.request("sdram_clock"), ClockSignal("sys_ps")) + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ @@ -57,7 +57,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cmd_latency=2) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, module = M12L64322A(sys_clk_freq, "1:1"), diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py index 79de83c..7435493 100755 --- a/litex_boards/targets/minispartan6.py +++ b/litex_boards/targets/minispartan6.py @@ -38,7 +38,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90) # SDRAM clock - self.specials += DDROutput(0, 1, platform.request("sdram_clock"), ClockSignal("sys_ps")) + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ @@ -54,7 +54,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cmd_latency=2) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, module = AS4C16M16(sys_clk_freq, "1:1"), diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index 450ca94..fa75121 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -10,6 +10,8 @@ import sys from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer +from litex.build.io import DDROutput + from litex_boards.platforms import ulx3s from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -45,7 +47,7 @@ class _CRG(Module): self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) # SDRAM clock - self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) # Prevent ESP32 from resetting FPGA self.comb += platform.request("wifi_gpio0").eq(1)