From 18b2758e4ec12ec0e3de80eb27c79c34634bcc10 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 30 Jun 2021 11:50:42 +0200 Subject: [PATCH] decklink_quad_hdmi_recorder: Add other DDR3 SDRAM modules building but untested. --- .../platforms/decklink_quad_hdmi_recorder.py | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/litex_boards/platforms/decklink_quad_hdmi_recorder.py b/litex_boards/platforms/decklink_quad_hdmi_recorder.py index 0453d60..ac262ad 100644 --- a/litex_boards/platforms/decklink_quad_hdmi_recorder.py +++ b/litex_boards/platforms/decklink_quad_hdmi_recorder.py @@ -75,20 +75,26 @@ _io = [ Subsignal("cas_n", Pins("AM16"), IOStandard("SSTL15_DCI")), Subsignal("we_n", Pins("AP15"), IOStandard("SSTL15_DCI")), Subsignal("cs_n", Pins("AM15"), IOStandard("SSTL15_DCI")), - Subsignal("dm", Pins("AH26 AN26"), + Subsignal("dm", Pins("AH26 AN26 AJ21 AM21 AH18 AE25 AD21 AD19"), IOStandard("SSTL15_DCI"), Misc("DATA_RATE=DDR")), Subsignal("dq", Pins( "AM27 AK28 AH27 AJ28 AK26 AH28 AM26 AK27", - "AP29 AP28 AM30 AN27 AM29 AN28 AL30 AL29"), + "AP29 AP28 AM30 AN27 AM29 AN28 AL30 AL29", + "AM20 AK22 AL20 AL22 AL23 AL24 AK23 AL25", + "AP25 AM24 AN24 AM22 AN23 AN22 AP24 AP23", + "AJ16 AG17 AG15 AG19 AH16 AH19 AG14 AG16", + "AJ24 AG24 AJ23 AF23 AH22 AF24 AH23 AG25", + "AE20 AF20 AD20 AG20 AE22 AE23 AF22 AG22", + "AF18 AD15 AF17 AE17 AF14 AE18 AF15 AD16"), IOStandard("SSTL15_DCI"), Misc("ODT=RTT_40"), Misc("DATA_RATE=DDR")), - Subsignal("dqs_p", Pins("AL27 AN29"), + Subsignal("dqs_p", Pins("AL27 AN29 AJ20 AP20 AJ15 AH24 AG21 AE16"), IOStandard("DIFF_SSTL15_DCI"), Misc("ODT=RTT_40"), Misc("DATA_RATE=DDR")), - Subsignal("dqs_n", Pins("AL28 AP30"), + Subsignal("dqs_n", Pins("AL28 AP30 AK20 AP21 AJ14 AJ25 AH21 AE15"), IOStandard("DIFF_SSTL15_DCI"), Misc("ODT=RTT_40"), Misc("DATA_RATE=DDR")),