diff --git a/litex_boards/platforms/xilinx_kv260.py b/litex_boards/platforms/xilinx_kv260.py
index 6a347f1..838259d 100644
--- a/litex_boards/platforms/xilinx_kv260.py
+++ b/litex_boards/platforms/xilinx_kv260.py
@@ -8,17 +8,22 @@ from litex.build.generic_platform import *
 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
 
 
+# IOs ----------------------------------------------------------------------------------------------
+
 _io = [
+    # Fan.
     ("fan", 0, Pins("A12"), IOStandard("LVCMOS33")),
-    # seems like there are no on-board clock sources for PL when PS is not used
-    # so here a clock-capable PMOD connector pin is added as a possible clock input (not tested)
+
+    # Seems like there are no on-board clock sources for PL when PS is not used so here a
+    # clock-capable PMOD connector pin is added as a possible clock input (not tested).
     ("pmod_hda16_cc", 0, Pins("B21"), IOStandard("LVCMOS33")),
 ]
 
+# Platform -----------------------------------------------------------------------------------------
 
 class Platform(XilinxPlatform):
-    default_clk_name = 'pmod_hda16_cc'
-    default_clk_period = 10.0
+    default_clk_name   = "pmod_hda16_cc"
+    default_clk_period = 1e9/100e6
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xck26-sfvc784-2lv-c", _io, toolchain="vivado")
@@ -31,4 +36,4 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment, *args, **kwargs):
         XilinxPlatform.do_finalize(self, fragment, *args, **kwargs)
-        self.add_period_constraint(self.lookup_request("pmod_hda16_cc", loose=True), self.default_clk_period)
+        self.add_period_constraint(self.lookup_request("pmod_hda16_cc", loose=True), 1e9/100e6)
diff --git a/litex_boards/targets/xilinx_kv260.py b/litex_boards/targets/xilinx_kv260.py
index a9de08e..c15f1ff 100644
--- a/litex_boards/targets/xilinx_kv260.py
+++ b/litex_boards/targets/xilinx_kv260.py
@@ -6,6 +6,16 @@
 # Copyright (c) 2022 Ilia Sergachev <ilia@sergachev.ch>
 # SPDX-License-Identifier: BSD-2-Clause
 
+# Build/Use:
+# The current support is sufficient to run LiteX BIOS on Cortex-A53 core #0:
+# ./xilinx_kv260.py --build --load
+# LiteX BIOS can then be executed on hardware using JTAG with the following xsct script from:
+# https://github.com/sergachev/litex-template/tree/kv260
+# make -f Makefile.kv260 load will build everything and run xsct in the end.
+#
+# Relies on https://github.com/lucaceresoli/zynqmp-pmufw-builder to create a generic PMU firmware;
+# first build will take a while because it includes a cross-toolchain.
+
 import argparse
 
 from migen import *
@@ -24,7 +34,6 @@ from litex.soc.integration.builder import *
 
 # CRG ----------------------------------------------------------------------------------------------
 
-
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
         self.rst = Signal()
@@ -45,7 +54,6 @@ class _CRG(Module):
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
-
 class BaseSoC(SoCCore):
     mem_map = {"csr": 0xA000_0000}  # default GP0 address on ZynqMP
 
@@ -60,7 +68,7 @@ class BaseSoC(SoCCore):
             ident = "LiteX SoC on KV260",
             **kwargs)
 
-        # ZynqMP Integration ---------------------------------------------------------------------
+        # ZynqMP Integration -----------------------------------------------------------------------
         if kwargs.get("cpu_type", None) == "zynqmp":
             self.cpu.config.update({
                 'PSU_MIO_36_DIRECTION': 'out',
@@ -202,7 +210,6 @@ class BaseSoC(SoCCore):
 
 # Build --------------------------------------------------------------------------------------------
 
-
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on KV260")
     parser.add_argument("--build",        action="store_true", help="Build bitstream.")