From 1969b4f6d3ccbe8d705e629cccb43b76747eed27 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Nov 2023 18:57:42 +0100 Subject: [PATCH] siglent_sds1104xe: Update Ethernet/Etherbone integration. --- litex_boards/targets/siglent_sds1104xe.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index 5164dcc..dbf8fa4 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -102,7 +102,8 @@ class BaseSoC(SoCCore): # Ethernet PHY self.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) + pads = self.platform.request("eth"), + ) # Etherbone. self.add_etherbone( @@ -111,10 +112,11 @@ class BaseSoC(SoCCore): mac_address = 0x10e2d5000001, data_width = 8, interface = "hybrid", - endianness = self.cpu.endianness) + endianness = self.cpu.endianness + ) # Software Interface. - ethmac = self.get_module("ethcore_etherbone").mac + self.ethmac = ethmac = self.get_module("ethcore_etherbone").mac ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)