From 19767e1a2aa62ce12f76107c862b0eedb1234ba7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 29 Jan 2021 09:30:54 +0100 Subject: [PATCH] platforms/fpc_iii: avoid using dummy pin on odt. Now possible with https://github.com/enjoy-digital/litedram/commit/2f5784432d2bd42686c91ea148fcb7849317cf5d. --- litex_boards/platforms/fpc_iii.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/fpc_iii.py b/litex_boards/platforms/fpc_iii.py index 5a781e6..353a674 100644 --- a/litex_boards/platforms/fpc_iii.py +++ b/litex_boards/platforms/fpc_iii.py @@ -101,7 +101,7 @@ _io = [ Misc("DIFFRESISTOR=100")), Subsignal("clk_p" , Pins("K16"), IOStandard("SSTL15D_I")), Subsignal("cke", Pins("D19"), IOStandard("SSTL15_I")), - Subsignal("odt", Pins("H4")), # FIXME not connected + #Subsignal("odt", Pins("")), Not connected. Subsignal("reset_n", Pins("L20"), IOStandard("SSTL15_I")), # Pseudo-VCCIO pads: SSTL15_II for 10 mA drive strength, see FPGA-TN-02035, section 6.7. Subsignal( "vccio", Pins( "C20 E16 J18 K18 L18 L19 N17 N18 T16" ),