From 348677598de36505ee373b8febc059070d2dad11 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Tue, 17 Sep 2019 17:06:23 +0800 Subject: [PATCH 1/4] targets: fomu: support building with a cpu Allow the user to specify a CPU. Signed-off-by: Sean Cross --- litex_boards/partner/targets/fomu.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/litex_boards/partner/targets/fomu.py b/litex_boards/partner/targets/fomu.py index 302ec08..546c13b 100755 --- a/litex_boards/partner/targets/fomu.py +++ b/litex_boards/partner/targets/fomu.py @@ -164,11 +164,13 @@ class BaseSoC(SoCCore): raise ValueError("unrecognized fomu board: {}".format(board)) platform = Platform() + if "cpu_type" not in kwargs: + kwargs["cpu_type"] = None + kwargs["cpu_variant"] = None + clk_freq = int(12e6) SoCCore.__init__(self, platform, clk_freq, - cpu_type=None, - cpu_variant=None, integrated_sram_size=0, with_uart=False, with_ctrl=False, From 218bd353c1b251500187208229096c7f7df4bd85 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Tue, 17 Sep 2019 17:07:26 +0800 Subject: [PATCH 2/4] targets: fomu: use memory array for sram address Use the memory array to find the address for the sram bank. Signed-off-by: Sean Cross --- litex_boards/partner/targets/fomu.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/partner/targets/fomu.py b/litex_boards/partner/targets/fomu.py index 546c13b..6fa6eff 100755 --- a/litex_boards/partner/targets/fomu.py +++ b/litex_boards/partner/targets/fomu.py @@ -182,7 +182,7 @@ class BaseSoC(SoCCore): # Use this as CPU RAM. spram_size = 128*1024 self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size) - self.register_mem("sram", 0x10000000, self.spram.bus, spram_size) + self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size) if usb_core is not None: # Add USB pads. We use DummyUsb, which simply enumerates as a USB From c8e8f254ca886353b36c0ad7806b4924fdc8ffd9 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Tue, 17 Sep 2019 17:08:05 +0800 Subject: [PATCH 3/4] targets: fomu: add USBSoC and default to heap placer The heap placer is important enough that we should just make it the default. Also, add a `USBSoC` that includes the required interrupt table, as this must be specified prior to calling `__init__()`. Signed-off-by: Sean Cross --- litex_boards/partner/targets/fomu.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/litex_boards/partner/targets/fomu.py b/litex_boards/partner/targets/fomu.py index 6fa6eff..04f2045 100755 --- a/litex_boards/partner/targets/fomu.py +++ b/litex_boards/partner/targets/fomu.py @@ -127,13 +127,8 @@ class BaseSoC(SoCCore): "csr": 0x60000000, # (default shadow @0xe0000000) } - interrupt_map = { - "usb": 3, - } - interrupt_map.update(SoCCore.interrupt_map) - def __init__(self, board, - pnr_placer=None, pnr_seed=0, usb_core="dummyusb", usb_bridge=False, + pnr_placer="heap", pnr_seed=0, usb_core="dummyusb", usb_bridge=False, **kwargs): """Create a basic SoC for Fomu. @@ -214,6 +209,14 @@ class BaseSoC(SoCCore): if pnr_placer is not None: platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(pnr_placer) +class USBSoC(BaseSoC): + """A SoC for Fomu with interrupts for a softcore CPU""" + + interrupt_map = { + "usb": 3, + } + interrupt_map.update(SoCCore.interrupt_map) + # Build -------------------------------------------------------------------------------------------- From c20c489d66a28f33d602852c3accbc0221d526da Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Fri, 27 Sep 2019 11:26:23 +0800 Subject: [PATCH 4/4] fomu-evt: add i2c pins Signed-off-by: Sean Cross --- litex_boards/partner/platforms/fomu_evt.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litex_boards/partner/platforms/fomu_evt.py b/litex_boards/partner/platforms/fomu_evt.py index 9836e79..4047967 100644 --- a/litex_boards/partner/platforms/fomu_evt.py +++ b/litex_boards/partner/platforms/fomu_evt.py @@ -54,7 +54,10 @@ _io = [ Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), Subsignal("dq", Pins("14 17 19 18"), IOStandard("LVCMOS33")), ), - + ("i2c", 0, + Subsignal("scl", Pins("12"), IOStandard("LVCMOS18")), + Subsignal("sda", Pins("20"), IOStandard("LVCMOS18")), + ), ] # Connectors ---------------------------------------------------------------------------------------