From 19e5366ad1ffe0ecd27818de4ece8288944e75d9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 31 Mar 2020 18:18:45 +0200 Subject: [PATCH] targets/colorlight_5a_75b: update sys/sys_ps phases. --- litex_boards/targets/colorlight_5a_75b.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py index 059e199..f3dc0e8 100755 --- a/litex_boards/targets/colorlight_5a_75b.py +++ b/litex_boards/targets/colorlight_5a_75b.py @@ -52,8 +52,8 @@ class _CRG(Module): self.submodules.pll = pll = ECP5PLL() pll.register_clkin(clk25, 25e6) - pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11) - pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n) # SDRAM clock