From 19eb5708de674cf35add20bb21e914a6d727a78f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 5 May 2020 13:16:02 +0200 Subject: [PATCH] platforms: make sure all traditional platforms have a create_programmer method. --- litex_boards/platforms/colorlight_5a_75b.py | 4 ++++ litex_boards/platforms/ecp5_evn.py | 3 +-- litex_boards/platforms/ecpix5.py | 4 ++++ litex_boards/platforms/minispartan6.py | 4 ++-- litex_boards/platforms/pipistrello.py | 4 ++-- litex_boards/platforms/trellisboard.py | 4 ++++ litex_boards/platforms/ulx3s.py | 4 ++++ litex_boards/platforms/versa_ecp5.py | 4 ++++ litex_boards/prog/openocd_ecpix5.cfg | 9 +++++++++ litex_boards/prog/openocd_evn_ecp5.cfg | 9 +++++++++ litex_boards/prog/openocd_trellisboard.cfg | 9 +++++++++ litex_boards/prog/openocd_versa_ecp5.cfg | 9 +++++++++ 12 files changed, 61 insertions(+), 6 deletions(-) create mode 100644 litex_boards/prog/openocd_ecpix5.cfg create mode 100644 litex_boards/prog/openocd_evn_ecp5.cfg create mode 100644 litex_boards/prog/openocd_trellisboard.cfg create mode 100644 litex_boards/prog/openocd_versa_ecp5.cfg diff --git a/litex_boards/platforms/colorlight_5a_75b.py b/litex_boards/platforms/colorlight_5a_75b.py index c808f0c..805e419 100644 --- a/litex_boards/platforms/colorlight_5a_75b.py +++ b/litex_boards/platforms/colorlight_5a_75b.py @@ -6,6 +6,7 @@ from litex.build.generic_platform import * from litex.build.lattice import LatticePlatform +from litex.build.lattice.programmer import OpenOCDJTAGProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -221,6 +222,9 @@ class Platform(LatticePlatform): connectors = {"6.1": _connectors_v6_1, "7.0": _connectors_v7_0}[revision] LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain="trellis") + def create_programmer(self): + return OpenOCDJTAGProgrammer("openocd_colorlight_5a_75b.cfg") + def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6) diff --git a/litex_boards/platforms/ecp5_evn.py b/litex_boards/platforms/ecp5_evn.py index 2d88f14..031c18b 100644 --- a/litex_boards/platforms/ecp5_evn.py +++ b/litex_boards/platforms/ecp5_evn.py @@ -136,8 +136,7 @@ class Platform(LatticePlatform): return LatticePlatform.request(self, *args, **kwargs) def create_programmer(self): - trellis = os.environ.get("TRELLIS", "/usr/share/trellis") - return OpenOCDJTAGProgrammer(os.path.join(trellis, "misc", "openocd", "ecp5-evn.cfg"), "bscan_spi_lfe5um5g85f.svf") + return OpenOCDJTAGProgrammer("openocd_evn_ecp5.cfg") def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/ecpix5.py b/litex_boards/platforms/ecpix5.py index b54f5fa..221fa06 100644 --- a/litex_boards/platforms/ecpix5.py +++ b/litex_boards/platforms/ecpix5.py @@ -3,6 +3,7 @@ from litex.build.generic_platform import * from litex.build.lattice import LatticePlatform +from litex.build.lattice.programmer import OpenOCDJTAGProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -97,6 +98,9 @@ class Platform(LatticePlatform): def __init__(self, **kwargs): LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG554I", _io, _connectors, **kwargs) + def create_programmer(self): + return OpenOCDJTAGProgrammer("openocd_ecpix5.cfg") + def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) diff --git a/litex_boards/platforms/minispartan6.py b/litex_boards/platforms/minispartan6.py index 18d4433..0ad7e07 100644 --- a/litex_boards/platforms/minispartan6.py +++ b/litex_boards/platforms/minispartan6.py @@ -3,7 +3,7 @@ from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform -from litex.build.xilinx.programmer import FpgaProg +from litex.build.xilinx.programmer import XC3SProg # IOs ---------------------------------------------------------------------------------------------- @@ -136,7 +136,7 @@ class Platform(XilinxPlatform): XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors) def create_programmer(self): - return FpgaProg() + return XC3SProg(cable="ftdi") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/pipistrello.py b/litex_boards/platforms/pipistrello.py index cbd7fd3..932b3e4 100644 --- a/litex_boards/platforms/pipistrello.py +++ b/litex_boards/platforms/pipistrello.py @@ -7,7 +7,7 @@ from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform -from litex.build.openocd import OpenOCD +from litex.build.xilinx.programmer import XC3SProg # IOs ---------------------------------------------------------------------------------------------- @@ -152,7 +152,7 @@ class Platform(XilinxPlatform): self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6" def create_programmer(self): - return OpenOCD("openocd_xilinx_xc6.cfg", "bscan_spi_xc6slx45.bit") + return XC3SProg(cable="ftdi") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/trellisboard.py b/litex_boards/platforms/trellisboard.py index 1fd1982..6487d60 100644 --- a/litex_boards/platforms/trellisboard.py +++ b/litex_boards/platforms/trellisboard.py @@ -3,6 +3,7 @@ from litex.build.generic_platform import * from litex.build.lattice import LatticePlatform +from litex.build.lattice.programmer import OpenOCDJTAGProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -220,6 +221,9 @@ class Platform(LatticePlatform): def __init__(self, **kwargs): LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG756C", _io, _connectors, **kwargs) + def create_programmer(self): + return OpenOCDJTAGProgrammer("openocd_trellisboard.cfg") + def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) diff --git a/litex_boards/platforms/ulx3s.py b/litex_boards/platforms/ulx3s.py index 661051d..f2859cb 100644 --- a/litex_boards/platforms/ulx3s.py +++ b/litex_boards/platforms/ulx3s.py @@ -3,6 +3,7 @@ from litex.build.generic_platform import * from litex.build.lattice import LatticePlatform +from litex.build.lattice.programmer import UJProg # IOs ---------------------------------------------------------------------------------------------- @@ -102,6 +103,9 @@ class Platform(LatticePlatform): def __init__(self, device="LFE5U-45F", **kwargs): LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs) + def create_programmer(self): + return UJProg() + def do_finalize(self, fragment): LatticePlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6) diff --git a/litex_boards/platforms/versa_ecp5.py b/litex_boards/platforms/versa_ecp5.py index 8c6682c..4ea3df4 100644 --- a/litex_boards/platforms/versa_ecp5.py +++ b/litex_boards/platforms/versa_ecp5.py @@ -4,6 +4,7 @@ from litex.build.generic_platform import * from litex.build.lattice import LatticePlatform +from litex.build.lattice.programmer import OpenOCDJTAGProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -223,6 +224,9 @@ class Platform(LatticePlatform): def __init__(self, **kwargs): LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs) + def create_programmer(self): + return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg") + def do_finalize(self, fragment): self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6) diff --git a/litex_boards/prog/openocd_ecpix5.cfg b/litex_boards/prog/openocd_ecpix5.cfg new file mode 100644 index 0000000..c52ab7c --- /dev/null +++ b/litex_boards/prog/openocd_ecpix5.cfg @@ -0,0 +1,9 @@ +interface ftdi +ftdi_vid_pid 0x0403 0x6010 +ftdi_channel 0 +ftdi_layout_init 0x00e8 0x60eb +reset_config none + +adapter_khz 25000 + +jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043 diff --git a/litex_boards/prog/openocd_evn_ecp5.cfg b/litex_boards/prog/openocd_evn_ecp5.cfg new file mode 100644 index 0000000..21e9bb4 --- /dev/null +++ b/litex_boards/prog/openocd_evn_ecp5.cfg @@ -0,0 +1,9 @@ +interface ftdi +ftdi_vid_pid 0x0403 0x6010 +ftdi_channel 0 +ftdi_layout_init 0xfff8 0xfffb +reset_config none + +adapter_khz 5000 + +jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043 diff --git a/litex_boards/prog/openocd_trellisboard.cfg b/litex_boards/prog/openocd_trellisboard.cfg new file mode 100644 index 0000000..21e9bb4 --- /dev/null +++ b/litex_boards/prog/openocd_trellisboard.cfg @@ -0,0 +1,9 @@ +interface ftdi +ftdi_vid_pid 0x0403 0x6010 +ftdi_channel 0 +ftdi_layout_init 0xfff8 0xfffb +reset_config none + +adapter_khz 5000 + +jtag newtap ecp5 tap -irlen 8 -expected-id 0x81113043 diff --git a/litex_boards/prog/openocd_versa_ecp5.cfg b/litex_boards/prog/openocd_versa_ecp5.cfg new file mode 100644 index 0000000..eaf00a1 --- /dev/null +++ b/litex_boards/prog/openocd_versa_ecp5.cfg @@ -0,0 +1,9 @@ +interface ftdi +ftdi_vid_pid 0x0403 0x6010 +ftdi_channel 0 +ftdi_layout_init 0xfff8 0xfffb +reset_config none + +adapter_khz 25000 + +jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043