From 1abb03e514840ddfbc7a541f88cba693d7a6fb09 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 24 Jan 2022 18:46:51 +0100 Subject: [PATCH] tang_nano_4k: Review/Cleanup: - Revert abstractions on clk_name/period: Too much abstraction to avoid duplications makes the code more difficult to read. ex: - When constraining clk27, frequency is already in the name. - In the target, we want to know we are using clk27 as the main clk. - We need a default sys_clk_freq for project only importing BaseSoC. - Revert SPI Flash import (for consistency with other targets). - Keep VexRiscv as default CPU since this target is able to run it and also for consistency with other targets. --- litex_boards/platforms/sipeed_tang_nano_4k.py | 11 +++++------ litex_boards/targets/sipeed_tang_nano_4k.py | 18 ++++++++---------- 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/litex_boards/platforms/sipeed_tang_nano_4k.py b/litex_boards/platforms/sipeed_tang_nano_4k.py index f31bb4e..b804914 100644 --- a/litex_boards/platforms/sipeed_tang_nano_4k.py +++ b/litex_boards/platforms/sipeed_tang_nano_4k.py @@ -83,9 +83,8 @@ _connectors = [ # Platform ----------------------------------------------------------------------------------------- class Platform(GowinPlatform): - default_clk_name = "clk27" - default_clk_freq = 27e6 - default_clk_period = 1e9 / default_clk_freq + default_clk_name = "clk27" + default_clk_period = 1e9/27e6 def __init__(self): GowinPlatform.__init__(self, "GW1NSR-LV4CQN48PC7/I6", _io, _connectors, toolchain="gowin", devicename="GW1NSR-4C") @@ -96,6 +95,6 @@ class Platform(GowinPlatform): def create_programmer(self): return OpenFPGALoader("tangnano4k") - def do_finalize(self, fragment, *args, **kwargs): - GowinPlatform.do_finalize(self, fragment, *args, **kwargs) - self.add_period_constraint(self.lookup_request("clk27", loose=True), 1e9 / self.default_clk_freq) + def do_finalize(self, fragment): + GowinPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk27", loose=True), 1e9/27e6) diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py index e0cf785..91cebfa 100755 --- a/litex_boards/targets/sipeed_tang_nano_4k.py +++ b/litex_boards/targets/sipeed_tang_nano_4k.py @@ -23,11 +23,8 @@ from litex_boards.platforms import tang_nano_4k from litehyperbus.core.hyperbus import HyperRAM -from litespi.modules import W25Q32 -from litespi.opcodes import SpiNorFlashOpCodes as Codes - kB = 1024 -MB = 1024 * kB +mB = 1024*kB # CRG ---------------------------------------------------------------------------------------------- @@ -39,13 +36,13 @@ class _CRG(Module): # # # # Clk / Rst - default_clk = platform.request(platform.default_clk_name) + clk27 = platform.request("clk27") rst_n = platform.request("user_btn", 0) # PLL self.submodules.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device) self.comb += pll.reset.eq(~rst_n) - pll.register_clkin(default_clk, platform.default_clk_freq) + pll.register_clkin(clk27, 27e6) pll.create_clkout(self.cd_sys, sys_clk_freq) @@ -53,7 +50,7 @@ class _CRG(Module): if with_video_pll: self.submodules.video_pll = video_pll = GW1NPLL(devicename=platform.devicename, device=platform.device) self.comb += video_pll.reset.eq(~rst_n) - video_pll.register_clkin(default_clk, platform.default_clk_freq) + video_pll.register_clkin(clk27, 27e6) self.clock_domains.cd_hdmi = ClockDomain() self.clock_domains.cd_hdmi5x = ClockDomain() video_pll.create_clkout(self.cd_hdmi5x, 125e6) @@ -67,7 +64,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq, with_hyperram=False, with_led_chaser=True, with_video_terminal=True, **kwargs): + def __init__(self, sys_clk_freq=int(27e6), with_hyperram=False, with_led_chaser=True, with_video_terminal=True, **kwargs): platform = tang_nano_4k.Platform() if "cpu_type" in kwargs and kwargs["cpu_type"] == "gowin_emcu": @@ -102,6 +99,8 @@ class BaseSoC(SoCCore): ) else: # SPI Flash -------------------------------------------------------------------------------- + from litespi.modules import W25Q32 + from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False) # Add ROM linker region -------------------------------------------------------------------- self.bus.add_region("rom", SoCRegion( @@ -125,7 +124,7 @@ class BaseSoC(SoCCore): self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk) self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk) self.submodules.hyperram = HyperRAM(hyperram_pads) - self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8*1024*1024)) + self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8*mB)) # Video ------------------------------------------------------------------------------------ if with_video_terminal: @@ -149,7 +148,6 @@ def main(): parser.add_argument("--sys-clk-freq",default=27e6, help="System clock frequency.") builder_args(parser) soc_core_args(parser) - parser.set_defaults(cpu_type="gowin_emcu") args = parser.parse_args() soc = BaseSoC(