diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py
index b144a7a..78c8a81 100755
--- a/litex_boards/targets/ac701.py
+++ b/litex_boards/targets/ac701.py
@@ -50,6 +50,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index 7212a54..a7dc5fd 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -66,6 +66,7 @@ class CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index e97fb30..fa96adc 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -50,6 +50,7 @@ class CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py
index d070eba..ad50674 100755
--- a/litex_boards/targets/alveo_u250.py
+++ b/litex_boards/targets/alveo_u250.py
@@ -44,6 +44,7 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk300", 0), 300e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py
index 0bc5025..94c8718 100755
--- a/litex_boards/targets/arty.py
+++ b/litex_boards/targets/arty.py
@@ -47,6 +47,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_eth, 25e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/arty_s7.py b/litex_boards/targets/arty_s7.py
index 6a06853..46f460b 100755
--- a/litex_boards/targets/arty_s7.py
+++ b/litex_boards/targets/arty_s7.py
@@ -45,6 +45,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/fk33.py b/litex_boards/targets/fk33.py
index 1d3740d..6ce4c69 100755
--- a/litex_boards/targets/fk33.py
+++ b/litex_boards/targets/fk33.py
@@ -38,6 +38,7 @@ class _CRG(Module):
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("clk200"), 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
# BaseSoC ------------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py
index c600d14..9d9d51c 100755
--- a/litex_boards/targets/genesys2.py
+++ b/litex_boards/targets/genesys2.py
@@ -41,6 +41,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py
index 6b612f6..1c30876 100755
--- a/litex_boards/targets/kc705.py
+++ b/litex_boards/targets/kc705.py
@@ -46,6 +46,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py
index 7ede656..f84707d 100755
--- a/litex_boards/targets/kcu105.py
+++ b/litex_boards/targets/kcu105.py
@@ -47,6 +47,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 200e6, with_reset=False)
pll.create_clkout(self.cd_eth, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py
index 0f743aa..504b913 100755
--- a/litex_boards/targets/kx2.py
+++ b/litex_boards/targets/kx2.py
@@ -39,6 +39,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/litefury.py b/litex_boards/targets/litefury.py
index 48e64bf..07a0b0d 100755
--- a/litex_boards/targets/litefury.py
+++ b/litex_boards/targets/litefury.py
@@ -50,6 +50,7 @@ class CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py
index 67f35c6..f1164a6 100755
--- a/litex_boards/targets/mercury_xu5.py
+++ b/litex_boards/targets/mercury_xu5.py
@@ -38,9 +38,9 @@ class _CRG(Module):
self.submodules.pll = pll = USMMCM(speedgrade=-1)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("clk100"), 100e6)
-
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py
index 63c53e1..2181fbb 100755
--- a/litex_boards/targets/mimas_a7.py
+++ b/litex_boards/targets/mimas_a7.py
@@ -45,6 +45,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py
index 452e8d6..4c0df18 100755
--- a/litex_boards/targets/minispartan6.py
+++ b/litex_boards/targets/minispartan6.py
@@ -55,6 +55,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
# SDRAM clock
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index fb7d840..7a37ef4 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -47,6 +47,7 @@ class CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py
index cf11687..10e0992 100755
--- a/litex_boards/targets/netv2.py
+++ b/litex_boards/targets/netv2.py
@@ -55,6 +55,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_clk100, 100e6)
pll.create_clkout(self.cd_eth, 50e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py
index 9e6e66a..35e336a 100755
--- a/litex_boards/targets/nexys4ddr.py
+++ b/litex_boards/targets/nexys4ddr.py
@@ -49,6 +49,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_eth, 50e6)
pll.create_clkout(self.cd_vga, 25e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py
index 6beea14..9cfa8d7 100755
--- a/litex_boards/targets/nexys_video.py
+++ b/litex_boards/targets/nexys_video.py
@@ -45,6 +45,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_clk100, 100e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py
index 57c1d2e..e9374ce 100755
--- a/litex_boards/targets/pano_logic_g2.py
+++ b/litex_boards/targets/pano_logic_g2.py
@@ -39,6 +39,7 @@ class _CRG(Module):
self.comb += pll.reset.eq(~platform.request("user_btn_n") | self.rst)
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_sys, clk_freq)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
# BaseSoC ------------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/redpitaya.py b/litex_boards/targets/redpitaya.py
index 6908d46..15f3ab0 100755
--- a/litex_boards/targets/redpitaya.py
+++ b/litex_boards/targets/redpitaya.py
@@ -41,6 +41,7 @@ class _CRG(Module):
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
pll.create_clkout(self.cd_sys, sys_clk_freq)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
# BaseSoC ------------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/sds1104xe.py b/litex_boards/targets/sds1104xe.py
index 8cd0d3a..46efde4 100755
--- a/litex_boards/targets/sds1104xe.py
+++ b/litex_boards/targets/sds1104xe.py
@@ -54,6 +54,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py
index f6999f4..3b1118f 100755
--- a/litex_boards/targets/tagus.py
+++ b/litex_boards/targets/tagus.py
@@ -51,6 +51,7 @@ class CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py
index 3c23dc0..a59beab 100755
--- a/litex_boards/targets/vc707.py
+++ b/litex_boards/targets/vc707.py
@@ -42,6 +42,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py
index efff26d..3585128 100755
--- a/litex_boards/targets/vcu118.py
+++ b/litex_boards/targets/vcu118.py
@@ -41,6 +41,7 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py
index 0cc47ec..85e6bb2 100755
--- a/litex_boards/targets/xcu1525.py
+++ b/litex_boards/targets/xcu1525.py
@@ -43,6 +43,7 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk300", ddram_channel), 300e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py
index e12caa4..63a9ad9 100755
--- a/litex_boards/targets/zcu104.py
+++ b/litex_boards/targets/zcu104.py
@@ -42,6 +42,7 @@ class _CRG(Module):
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/zybo_z7.py b/litex_boards/targets/zybo_z7.py
index db59bfb..971ef69 100755
--- a/litex_boards/targets/zybo_z7.py
+++ b/litex_boards/targets/zybo_z7.py
@@ -39,7 +39,8 @@ class _CRG(Module):
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("clk125"), 125e6)
- pll.create_clkout(self.cd_sys, sys_clk_freq)
+ pll.create_clkout(self.cd_sys, sys_clk_freq)
+ platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
# BaseSoC ------------------------------------------------------------------------------------------