From 1ae26dd499f80337830678079a43ba17d2a8f29d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 30 Oct 2019 16:35:32 +0100 Subject: [PATCH] targets: use type="io" instead of io_region=True --- litex_boards/community/targets/ac701.py | 2 +- litex_boards/official/targets/arty.py | 2 +- litex_boards/official/targets/genesys2.py | 2 +- litex_boards/official/targets/kc705.py | 2 +- litex_boards/official/targets/kcu105.py | 2 +- litex_boards/official/targets/nexys4ddr.py | 2 +- litex_boards/official/targets/nexys_video.py | 2 +- litex_boards/official/targets/simple.py | 2 +- litex_boards/official/targets/versa_ecp5.py | 2 +- litex_boards/partner/targets/c10lprefkit.py | 2 +- litex_boards/partner/targets/netv2.py | 2 +- litex_boards/partner/targets/trellisboard.py | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/litex_boards/community/targets/ac701.py b/litex_boards/community/targets/ac701.py index 7e745c4..50b5cc3 100755 --- a/litex_boards/community/targets/ac701.py +++ b/litex_boards/community/targets/ac701.py @@ -123,7 +123,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/arty.py b/litex_boards/official/targets/arty.py index 6ccd8f0..ff3f380 100755 --- a/litex_boards/official/targets/arty.py +++ b/litex_boards/official/targets/arty.py @@ -86,7 +86,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/genesys2.py b/litex_boards/official/targets/genesys2.py index 0c6a664..eaba489 100755 --- a/litex_boards/official/targets/genesys2.py +++ b/litex_boards/official/targets/genesys2.py @@ -78,7 +78,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/kc705.py b/litex_boards/official/targets/kc705.py index f1ac9e7..10af04a 100755 --- a/litex_boards/official/targets/kc705.py +++ b/litex_boards/official/targets/kc705.py @@ -80,7 +80,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/kcu105.py b/litex_boards/official/targets/kcu105.py index 707423a..a4f527b 100755 --- a/litex_boards/official/targets/kcu105.py +++ b/litex_boards/official/targets/kcu105.py @@ -117,7 +117,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py index bcc0f27..d43d2e7 100755 --- a/litex_boards/official/targets/nexys4ddr.py +++ b/litex_boards/official/targets/nexys4ddr.py @@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/nexys_video.py b/litex_boards/official/targets/nexys_video.py index 31294e1..16888c7 100755 --- a/litex_boards/official/targets/nexys_video.py +++ b/litex_boards/official/targets/nexys_video.py @@ -83,7 +83,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/simple.py b/litex_boards/official/targets/simple.py index b615a66..dea752d 100755 --- a/litex_boards/official/targets/simple.py +++ b/litex_boards/official/targets/simple.py @@ -44,7 +44,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/versa_ecp5.py b/litex_boards/official/targets/versa_ecp5.py index c7d6541..34799e6 100755 --- a/litex_boards/official/targets/versa_ecp5.py +++ b/litex_boards/official/targets/versa_ecp5.py @@ -118,7 +118,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/partner/targets/c10lprefkit.py b/litex_boards/partner/targets/c10lprefkit.py index 1bb2f51..b27e666 100755 --- a/litex_boards/partner/targets/c10lprefkit.py +++ b/litex_boards/partner/targets/c10lprefkit.py @@ -123,7 +123,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/partner/targets/netv2.py b/litex_boards/partner/targets/netv2.py index 1364b1d..b1f92a5 100755 --- a/litex_boards/partner/targets/netv2.py +++ b/litex_boards/partner/targets/netv2.py @@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/partner/targets/trellisboard.py b/litex_boards/partner/targets/trellisboard.py index dbf1a86..a0ef55e 100755 --- a/litex_boards/partner/targets/trellisboard.py +++ b/litex_boards/partner/targets/trellisboard.py @@ -120,7 +120,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac")