From 1c52e6b8fbea800c42327d5af4414cb43ec0b16e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 27 Jul 2021 19:30:38 +0200 Subject: [PATCH] targets/digilent_arty/spiflash: LiteSPI integration now provided by LiteX. --- litex_boards/targets/digilent_arty.py | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index e4281ed..9e8e690 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -27,11 +27,6 @@ from litedram.phy import s7ddrphy from liteeth.phy.mii import LiteEthPHYMII -from litespi.modules import S25FL128L -from litespi.opcodes import SpiNorFlashOpCodes as Codes -from litespi.phy.generic import LiteSPIPHY -from litespi import LiteSPI - # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -105,10 +100,9 @@ class BaseSoC(SoCCore): # Flash (through LiteSPI, experimental). if with_mapped_flash: - self.submodules.spiflash_phy = LiteSPIPHY(platform.request("spiflash4x"), S25FL128L(Codes.READ_1_1_4)) - self.submodules.spiflash_mmap = LiteSPI(self.spiflash_phy, clk_freq=sys_clk_freq, mmap_endianness=self.cpu.endianness) - spiflash_region = SoCRegion(origin=self.mem_map.get("spiflash", None), size=S25FL128L.total_size, cached=False) - self.bus.add_slave(name="spiflash", slave=self.spiflash_mmap.bus, region=spiflash_region) + from litespi.modules import S25FL128L + from litespi.opcodes import SpiNorFlashOpCodes as Codes + self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), with_master=True) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: