From 1dbecf704d52afc1084d16d231807f057b1d95b3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 11 Sep 2024 09:10:48 +0200 Subject: [PATCH] efinix_ti375: Cosmetic cleanups on #610. --- .../platforms/efinix_ti375_c529_dev_kit.py | 76 ++- .../targets/efinix_ti375_c529_dev_kit.py | 442 +++++++++--------- 2 files changed, 257 insertions(+), 261 deletions(-) diff --git a/litex_boards/platforms/efinix_ti375_c529_dev_kit.py b/litex_boards/platforms/efinix_ti375_c529_dev_kit.py index 8dccf5f..78cbded 100644 --- a/litex_boards/platforms/efinix_ti375_c529_dev_kit.py +++ b/litex_boards/platforms/efinix_ti375_c529_dev_kit.py @@ -1,8 +1,7 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2021 Franck Jullien -# Copyright (c) 2021 Florent Kermarrec +# Copyright (c) 2024 Dolu1990 # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * @@ -12,51 +11,43 @@ from litex.build.efinix import EfinixProgrammer # IOs ---------------------------------------------------------------------------------------------- _io = [ - # Clk - ("clk25", None, Pins("L17"), IOStandard("1.8_V_LVCMOS")), - ("clk100", None, Pins("U4"), IOStandard("3.3_V_LVCMOS")), + # Clk. + ("clk25", 0, Pins("L17"), IOStandard("1.8_V_LVCMOS")), + ("clk100", 0, Pins("U4"), IOStandard("3.3_V_LVCMOS")), - # Serial + # Serial. ("serial", 0, - Subsignal("tx", Pins("E9")), - Subsignal("rx", Pins("E10")), - IOStandard("3.3_V_LVTTL"), Misc("WEAK_PULLUP") - ), + Subsignal("tx", Pins(" E9")), + Subsignal("rx", Pins("E10")), + IOStandard("3.3_V_LVTTL"), + Misc("WEAK_PULLUP"), + ), - # Buttons + # Buttons. ("user_btn", 0, Pins("U19"), IOStandard("3.3_V_LVCMOS")), # DRAM. ("dram_pll_refclk", 0, Pins("XXX"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), - # SD-Card + # SDCard. ("spisdcard", 0, - Subsignal("clk", Pins("C9")), - Subsignal("mosi", Pins("C10")), - Subsignal("cs_n", Pins("A9")), - Subsignal("miso", Pins("B9")), - IOStandard("3.3_V_LVCMOS"), - ), + Subsignal("clk", Pins(" C9")), + Subsignal("mosi", Pins("C10")), + Subsignal("cs_n", Pins(" A9")), + Subsignal("miso", Pins(" B9")), + IOStandard("3.3_V_LVCMOS"), + ), ("sdcard", 0, - Subsignal("data", Pins("B9 B10 A8 A9")), - Subsignal("cmd", Pins("C10")), - Subsignal("clk", Pins("C9")) , #, Misc("SLEWRATE=1"), Misc("DRIVE_STRENGTH=16") - IOStandard("3.3_V_LVTTL"), - ), - - # SD-Card through PMOD2 - # ("sdcard", 0, - # Subsignal("data", Pins("F13 F14 E11 E14"), Misc("WEAK_PULLUP")), - # Subsignal("cmd", Pins("E16"), Misc("WEAK_PULLUP")), - # Subsignal("clk", Pins("E15")), - # IOStandard("3.3_V_LVCMOS"), - # ), + Subsignal("data", Pins("B9 B10 A8 A9")), + Subsignal("cmd", Pins("C10")), + Subsignal("clk", Pins("C9")) , #, Misc("SLEWRATE=1"), Misc("DRIVE_STRENGTH=16") + IOStandard("3.3_V_LVTTL"), + ), + # FAN. ("fan_speed_control", 0, Pins("T19"), IOStandard("3.3_V_LVCMOS")), ] - - # Bank voltage --------------------------------------------------------------------------------------- _bank_info = [ @@ -85,12 +76,12 @@ _connectors = [ ("pmod2", "E14 E16 F13 E15 F14 E11 F11 D11"), ["p1", "---", # 0 - # 3V3 5V GND GND GND GND GND GND ↓ - "--- B21 --- A21 --- --- C22 E21 B22 D21 --- --- B23 F21 A22 F22 --- --- D22 G21", - # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ↑ - # 21 22 23 24 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 ↓ - "D23 G22 --- --- F23 H20 E23 G20 --- --- H22 K23 H23 L23 --- --- L19 M21 M19 M22", - # GND GND GND GND GND GND ↑ + # 3V3 5V GND GND GND GND GND GND ↓ + "--- B21 --- A21 --- --- C22 E21 B22 D21 --- --- B23 F21 A22 F22 --- --- D22 G21", + # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ↑ + # 21 22 23 24 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 ↓ + "D23 G22 --- --- F23 H20 E23 G20 --- --- H22 K23 H23 L23 --- --- L19 M21 M19 M22", + # GND GND GND GND GND GND ↑ ], ] @@ -98,6 +89,7 @@ _connectors = [ def raw_pmod_io(pmod): return [(pmod, 0, Pins(" ".join([f"{pmod}:{i:d}" for i in range(8)])), IOStandard("3.3_V_LVTTL_/_LVCMOS"))] + def jtag_pmod_io(pmod): return [ ("usb_uart", 0, @@ -108,12 +100,15 @@ def jtag_pmod_io(pmod): IOStandard("3.3_V_LVCMOS") ), ] + def hdmi_px(px): return [ ("hdmi_i2c", 0, Subsignal("sda", Pins(f"{px}:26")), Subsignal("scl", Pins(f"{px}:28")), - IOStandard("1.8_V_LVCMOS"), Misc("WEAK_PULLUP"), Misc("SCHMITT_TRIGGER") + IOStandard("1.8_V_LVCMOS"), + Misc("WEAK_PULLUP"), + Misc("SCHMITT_TRIGGER"), ), ("hdmi_data", 0, Subsignal("clk", Pins(f"{px}:4")), @@ -127,6 +122,7 @@ def hdmi_px(px): IOStandard("1.8_V_LVCMOS") ), ] + # Platform ----------------------------------------------------------------------------------------- class Platform(EfinixPlatform): diff --git a/litex_boards/targets/efinix_ti375_c529_dev_kit.py b/litex_boards/targets/efinix_ti375_c529_dev_kit.py index 028693e..6b0f2b2 100755 --- a/litex_boards/targets/efinix_ti375_c529_dev_kit.py +++ b/litex_boards/targets/efinix_ti375_c529_dev_kit.py @@ -3,8 +3,7 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2021 Franck Jullien -# Copyright (c) 2021 Florent Kermarrec +# Copyright (c) 2024 Dolu1990 # SPDX-License-Identifier: BSD-2-Clause from migen import * @@ -12,24 +11,25 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.gen import * +from litex.build.io import DDROutput, SDROutput, SDRTristate +from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard + from litex_boards.platforms import efinix_ti375_c529_dev_kit -from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.soc import SoCRegion from litex.soc.integration.builder import * -from litex.soc.cores.led import LedChaser + from litex.soc.interconnect import axi + +from litex.soc.cores.clock import * +from litex.soc.cores.led import LedChaser from litex.soc.cores.bitbang import I2CMaster from litex.soc.cores.pwm import PWM +from litex.soc.cores.usb_ohci import USBOHCI from liteeth.phy.trionrgmii import LiteEthPHYRGMII -from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard -from litex.soc.cores.usb_ohci import USBOHCI -from litex.soc.integration.soc import SoCRegion -from litex.build.io import DDROutput -from litex.build.io import SDROutput -from litex.build.io import SDRTristate + # Full stream debian demo : # --cpu-type=vexiiriscv --cpu-variant=debian --update-repo=no --with-jtag-tap --with-sdcard --with-coherent-dma --with-ohci --vexii-video "name=video" # --vexii-args="--fetch-l1-hardware-prefetch=nl --fetch-l1-refill-count=2 --fetch-l1-mem-data-width-min=128 --lsu-l1-mem-data-width-min=128 --lsu-software-prefetch --lsu-hardware-prefetch rpt --performance-counters 9 --lsu-l1-store-buffer-ops=32 --lsu-l1-refill-count 4 --lsu-l1-writeback-count 4 --lsu-l1-store-buffer-slots=4 --relaxed-div" @@ -40,17 +40,18 @@ from litex.build.io import SDRTristate class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq, cpu_clk_freq): #self.rst = Signal() - self.cd_sys = ClockDomain() - self.cd_usb = ClockDomain() - self.cd_video = ClockDomain() - self.cd_cpu = ClockDomain() + self.cd_sys = ClockDomain() + self.cd_usb = ClockDomain() + self.cd_video = ClockDomain() + self.cd_cpu = ClockDomain() # # # + # Clk/Rst. clk100 = platform.request("clk100") - rst_n = platform.request("user_btn", 0) + rst_n = platform.request("user_btn", 0) - # PLL + # PLL. self.pll = pll = TITANIUMPLL(platform) self.comb += pll.reset.eq(~rst_n) pll.register_clkin(clk100, 100e6) @@ -59,9 +60,9 @@ class _CRG(LiteXModule): # this range, you should dedicate one unused clock for CLKOUT0. pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) pll.create_clkout(self.cd_cpu, cpu_clk_freq) - pll.create_clkout(self.cd_usb, 60e6, margin=0) - pll.create_clkout(None, 800e6) # LPDDR4 ctrl - pll.create_clkout(self.cd_video, 40e6) + pll.create_clkout(self.cd_usb, 60e6, margin=0) + pll.create_clkout(None, 800e6) # LPDDR4 ctrl + pll.create_clkout(self.cd_video, 40e6) platform.add_false_path_constraints(self.cd_cpu.clk, self.cd_usb.clk) platform.add_false_path_constraints(self.cd_cpu.clk, self.cd_sys.clk) platform.add_false_path_constraints(self.cd_cpu.clk, self.cd_video.clk) @@ -72,13 +73,10 @@ class _CRG(LiteXModule): class BaseSoC(SoCCore): mem_map = {**SoCCore.mem_map, **{ - "usb_ohci": 0xE0000000, + "usb_ohci": 0xe0000000, }} - def __init__(self, sys_clk_freq=100e6, - cpu_clk_freq=100e6, - with_ohci=False, - **kwargs): + def __init__(self, sys_clk_freq=100e6, cpu_clk_freq=100e6, with_ohci=False, **kwargs): platform = efinix_ti375_c529_dev_kit.Platform() # CRG -------------------------------------------------------------------------------------- @@ -87,21 +85,20 @@ class BaseSoC(SoCCore): # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Ti375 C529 Dev Kit", **kwargs) + if hasattr(self.cpu, "cpu_clk"): + self.comb += self.cpu.cpu_clk.eq(self.crg.cd_cpu.clk) + # Fan -------------------------------------------------------------------------------------- self.fan_pwm = PWM( pwm=platform.request("fan_speed_control", 0), with_csr = True, default_enable = 1, - default_width= 0x800, - default_period = 0xFFF + default_width = 0x800, + default_period = 0xfff, ) - if hasattr(self.cpu, "cpu_clk"): - self.comb += self.cpu.cpu_clk.eq(self.crg.cd_cpu.clk) - - # OHCI + # USB OHCI --------------------------------------------------------------------------------- if with_ohci: - _usb_pmod_ios = [ ("usb_pmod1", 0, Subsignal("dp", Pins("pmod1:0", "pmod1:1", "pmod1:2", "pmod1:3")), @@ -115,25 +112,28 @@ class BaseSoC(SoCCore): self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma) self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt) - # JTAG + # JTAG ------------------------------------------------------------------------------------- if hasattr(self.cpu, "jtag_clk"): _jtag_io = [ ("jtag", 0, - Subsignal("tck", Pins("pmod0:0")), - Subsignal("tdi", Pins("pmod0:1")), - Subsignal("tdo", Pins("pmod0:2")), - Subsignal("tms", Pins("pmod0:3")), - IOStandard("3.3_V_LVCMOS"), - ) + Subsignal("tck", Pins("pmod0:0")), + Subsignal("tdi", Pins("pmod0:1")), + Subsignal("tdo", Pins("pmod0:2")), + Subsignal("tms", Pins("pmod0:3")), + IOStandard("3.3_V_LVCMOS"), + ) ] self.platform.add_extension(_jtag_io) jtag_pads = platform.request("jtag") - self.comb += self.cpu.jtag_clk.eq(jtag_pads.tck) - self.comb += self.cpu.jtag_tms.eq(jtag_pads.tms) - self.comb += self.cpu.jtag_tdi.eq(jtag_pads.tdi) - self.comb += jtag_pads.tdo.eq(self.cpu.jtag_tdo) + self.comb += [ + self.cpu.jtag_clk.eq(jtag_pads.tck), + self.cpu.jtag_tms.eq(jtag_pads.tms), + self.cpu.jtag_tdi.eq(jtag_pads.tdi), + jtag_pads.tdo.eq(self.cpu.jtag_tdo), + ] platform.add_false_path_constraints(self.crg.cd_sys.clk, jtag_pads.tck) + # HDMI ------------------------------------------------------------------------------------- if hasattr(self.cpu, "video_clk"): _hdmi_io = efinix_ti375_c529_dev_kit.hdmi_px("p1") self.platform.add_extension(_hdmi_io) @@ -197,8 +197,8 @@ class BaseSoC(SoCCore): clk_video = self.crg.cd_video.clk self.comb += self.cpu.video_clk.eq(self.crg.cd_video.clk) video_data = platform.request("hdmi_data") - self.specials += DDROutput(i1=Signal(reset=0b0), i2=Signal(reset=0b1), o=video_data.clk, clk=clk_video) - self.specials += DDROutput(i1=self.cpu.video_color_en, i2=self.cpu.video_color_en, o=video_data.de, clk=clk_video) + self.specials += DDROutput(i1=Signal(reset=0b0), i2=Signal(reset=0b1), o=video_data.clk, clk=clk_video) + self.specials += DDROutput(i1=self.cpu.video_color_en, i2=self.cpu.video_color_en, o=video_data.de, clk=clk_video) for i in range(self.cpu.video_color.nbits): self.specials += DDROutput(i1=self.cpu.video_color[i], i2=self.cpu.video_color[i], o=video_data.d[i], clk=clk_video) @@ -250,57 +250,57 @@ class BaseSoC(SoCCore): ddr_info = root.find("efxpt:ddr_info", namespaces) ddr = et.SubElement(ddr_info, "efxpt:adv_ddr", - name = "ddr_inst1", - ddr_def = "DDR_0", - clkin_sel="0", - data_width="32", - physical_rank="1", - mem_type="LPDDR4x", - mem_density="8G" + name = "ddr_inst1", + ddr_def = "DDR_0", + clkin_sel = "0", + data_width = "32", + physical_rank = "1", + mem_type = "LPDDR4x", + mem_density = "8G", ) axi_target0 = et.SubElement(ddr, "efxpt:axi_target0",is_axi_width_256="false", is_axi_enable="true") gen_pin_target0 = et.SubElement(axi_target0, "efxpt:gen_pin_axi") - et.SubElement(gen_pin_target0, "efxpt:pin", name=axi_clk, type_name=f"ACLK_0", is_bus="false", is_clk="true", is_clk_invert="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_apcmd", type_name="ARAPCMD_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_ready", type_name="ARREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_valid", type_name="ARVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_qos", type_name="ARQOS_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_apcmd", type_name="AWAPCMD_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name=axi_clk, type_name=f"ACLK_0", is_bus="false", is_clk="true", is_clk_invert="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_apcmd", type_name="ARAPCMD_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_ready", type_name="ARREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_valid", type_name="ARVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_qos", type_name="ARQOS_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_apcmd", type_name="AWAPCMD_0", is_bus="false") et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_allstrb", type_name="AWALLSTRB_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awcobuf", type_name="AWCOBUF_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_ready", type_name="AWREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_valid", type_name="AWVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_lock", type_name="AWLOCK_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_qos", type_name="AWQOS_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_ready", type_name="BREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_valid", type_name="BVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_last", type_name="RLAST_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_ready", type_name="RREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_valid", type_name="RVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_last", type_name="WLAST_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_ready", type_name="WREADY_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_valid", type_name="WVALID_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_addr", type_name="ARADDR_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_burst", type_name="ARBURST_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_id", type_name="ARID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_len", type_name="ARLEN_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_size", type_name="ARSIZE_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_lock", type_name="ARLOCK_0", is_bus="false") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_addr", type_name="AWADDR_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_burst", type_name="AWBURST_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_id", type_name="AWID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_len", type_name="AWLEN_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_size", type_name="AWSIZE_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_cache", type_name="AWCACHE_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_id", type_name="BID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_resp", type_name="BRESP_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_data", type_name="RDATA_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_id", type_name="RID_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_resp", type_name="RRESP_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_data", type_name="WDATA_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_strb", type_name="WSTRB_0", is_bus="true") - et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_resetn", type_name="ARSTN_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_awcobuf", type_name="AWCOBUF_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_ready", type_name="AWREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_valid", type_name="AWVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_lock", type_name="AWLOCK_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_qos", type_name="AWQOS_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_ready", type_name="BREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_valid", type_name="BVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_last", type_name="RLAST_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_ready", type_name="RREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_valid", type_name="RVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_last", type_name="WLAST_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_ready", type_name="WREADY_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_valid", type_name="WVALID_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_addr", type_name="ARADDR_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_burst", type_name="ARBURST_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_id", type_name="ARID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_len", type_name="ARLEN_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_size", type_name="ARSIZE_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_ar_lock", type_name="ARLOCK_0", is_bus="false") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_addr", type_name="AWADDR_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_burst", type_name="AWBURST_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_id", type_name="AWID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_len", type_name="AWLEN_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_size", type_name="AWSIZE_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_aw_cache", type_name="AWCACHE_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_id", type_name="BID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_b_resp", type_name="BRESP_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_data", type_name="RDATA_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_id", type_name="RID_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_r_resp", type_name="RRESP_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_data", type_name="WDATA_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_w_strb", type_name="WSTRB_0", is_bus="true") + et.SubElement(gen_pin_target0, "efxpt:pin", name="ddr0_resetn", type_name="ARSTN_0", is_bus="false") axi_target1 = et.SubElement(ddr, "efxpt:axi_target1",is_axi_width_256="false", is_axi_enable="false") gen_pin_target1 = et.SubElement(axi_target1, "efxpt:gen_pin_axi") @@ -347,126 +347,126 @@ class BaseSoC(SoCCore): gen_pin_controller = et.SubElement(ddr, "efxpt:gen_pin_controller") et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_CLK", is_bus="false", is_clk="true", is_clk_invert="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_INT", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_MEM_RST_VALID", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_REFRESH", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_BUSY", is_bus="false") + et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_INT", is_bus="false") + et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_MEM_RST_VALID", is_bus="false") + et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_REFRESH", is_bus="false") + et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_BUSY", is_bus="false") et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_CMD_Q_ALMOST_FULL", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_DP_IDLE", is_bus="false") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_CKE", is_bus="true") - et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_PORT_BUSY", is_bus="true") + et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_DP_IDLE", is_bus="false") + et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_CKE", is_bus="true") + et.SubElement(gen_pin_controller,"efxpt:pin", name="", type_name="CTRL_PORT_BUSY", is_bus="true") gen_pin_cfg_ctrl = et.SubElement(ddr, "efxpt:gen_pin_cfg_ctrl") - et.SubElement(gen_pin_cfg_ctrl,"efxpt:pin", name="cfg_done", type_name="CFG_DONE", is_bus="false") + et.SubElement(gen_pin_cfg_ctrl,"efxpt:pin", name="cfg_done", type_name="CFG_DONE", is_bus="false") et.SubElement(gen_pin_cfg_ctrl,"efxpt:pin", name="cfg_start", type_name="CFG_START", is_bus="false") et.SubElement(gen_pin_cfg_ctrl,"efxpt:pin", name="cfg_reset", type_name="CFG_RESET", is_bus="false") - et.SubElement(gen_pin_cfg_ctrl,"efxpt:pin", name="cfg_sel", type_name="CFG_SEL", is_bus="false") + et.SubElement(gen_pin_cfg_ctrl,"efxpt:pin", name="cfg_sel", type_name="CFG_SEL", is_bus="false") ctrl_reg_inf = et.SubElement(ddr, "efxpt:ctrl_reg_inf", is_reg_ena= "false") gen_pin_ctrl_reg_inf = et.SubElement(ctrl_reg_inf, "efxpt:gen_pin_ctrl_reg_inf") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="axi0_ACLK", type_name="CR_ACLK", is_bus="false", is_clk="true", is_clk_invert="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARESETn", type_name="CR_ARESETN", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARVALID", type_name="CR_ARVALID", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARREADY", type_name="CR_ARREADY", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWVALID", type_name="CR_AWVALID", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWREADY", type_name="CR_AWREADY", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBVALID", type_name="CR_BVALID", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBREADY", type_name="CR_BREADY", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRLAST", type_name="CR_RLAST", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRVALID", type_name="CR_RVALID", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRREADY", type_name="CR_RREADY", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWLAST", type_name="CR_WLAST", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWVALID", type_name="CR_WVALID", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWREADY", type_name="CR_WREADY", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARADDR", type_name="CR_ARADDR", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARID", type_name="CR_ARID", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARLEN", type_name="CR_ARLEN", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARSIZE", type_name="CR_ARSIZE", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARBURST", type_name="CR_ARBURST", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWADDR", type_name="CR_AWADDR", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWID", type_name="CR_AWID", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWLEN", type_name="CR_AWLEN", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWSIZE", type_name="CR_AWSIZE", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWBURST", type_name="CR_AWBURST", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBID", type_name="CR_BID", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBRESP", type_name="CR_BRESP", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRDATA", type_name="CR_RDATA", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRID", type_name="CR_RID", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRRESP", type_name="CR_RRESP", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWDATA", type_name="CR_WDATA", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWSTRB", type_name="CR_WSTRB", is_bus="true") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="" ,type_name="CFG_PHY_RSTN", is_bus="false") - et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="" ,type_name="CTRL_RSTN", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="axi0_ACLK", type_name="CR_ACLK", is_bus="false", is_clk="true", is_clk_invert="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARESETn", type_name="CR_ARESETN", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARVALID", type_name="CR_ARVALID", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARREADY", type_name="CR_ARREADY", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWVALID", type_name="CR_AWVALID", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWREADY", type_name="CR_AWREADY", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBVALID", type_name="CR_BVALID", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBREADY", type_name="CR_BREADY", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRLAST", type_name="CR_RLAST", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRVALID", type_name="CR_RVALID", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRREADY", type_name="CR_RREADY", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWLAST", type_name="CR_WLAST", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWVALID", type_name="CR_WVALID", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWREADY", type_name="CR_WREADY", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARADDR", type_name="CR_ARADDR", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARID", type_name="CR_ARID", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARLEN", type_name="CR_ARLEN", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARSIZE", type_name="CR_ARSIZE", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regARBURST", type_name="CR_ARBURST", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWADDR", type_name="CR_AWADDR", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWID", type_name="CR_AWID", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWLEN", type_name="CR_AWLEN", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWSIZE", type_name="CR_AWSIZE", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regAWBURST", type_name="CR_AWBURST", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBID", type_name="CR_BID", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regBRESP", type_name="CR_BRESP", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRDATA", type_name="CR_RDATA", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRID", type_name="CR_RID", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regRRESP", type_name="CR_RRESP", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWDATA", type_name="CR_WDATA", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="regWSTRB", type_name="CR_WSTRB", is_bus="true") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="" , type_name="CFG_PHY_RSTN", is_bus="false") + et.SubElement(gen_pin_ctrl_reg_inf,"efxpt:pin", name="" , type_name="CTRL_RSTN", is_bus="false") cs_fpga = et.SubElement(ddr, "efxpt:cs_fpga") - et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLDOWN_DRV", value="34.3", value_type="str") - et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLDOWN_ODT", value="60", value_type="str") - et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLUP_DRV", value="34.3", value_type="str") - et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLUP_ODT", value="Hi-Z", value_type="str") - et.SubElement(cs_fpga,"efxpt:param", name="FPGA_VREF_RANGE0", value="22.040", value_type="float") - et.SubElement(cs_fpga,"efxpt:param", name="FPGA_VREF_RANGE1", value="23.000", value_type="float") - et.SubElement(cs_fpga,"efxpt:param", name="MEM_FPGA_VREF_RANGE", value="Range 1", value_type="str") + et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLDOWN_DRV", value="34.3", value_type="str") + et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLDOWN_ODT", value="60", value_type="str") + et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLUP_DRV", value="34.3", value_type="str") + et.SubElement(cs_fpga,"efxpt:param", name="DQ_PULLUP_ODT", value="Hi-Z", value_type="str") + et.SubElement(cs_fpga,"efxpt:param", name="FPGA_VREF_RANGE0", value="22.040", value_type="float") + et.SubElement(cs_fpga,"efxpt:param", name="FPGA_VREF_RANGE1", value="23.000", value_type="float") + et.SubElement(cs_fpga,"efxpt:param", name="MEM_FPGA_VREF_RANGE", value="Range 1", value_type="str") cs_memory = et.SubElement(ddr, "efxpt:cs_memory") - et.SubElement(cs_memory,"efxpt:param", name="BLEN", value="BL=16 Sequential", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="CA_ODT_CS0", value="RZQ/4", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="CA_ODT_CS1", value="Disable", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="CA_VREF_RANGE0", value="27.200", value_type="float") - et.SubElement(cs_memory,"efxpt:param", name="CA_VREF_RANGE1", value="22.000", value_type="float") - et.SubElement(cs_memory,"efxpt:param", name="DQ_ODT_CS0", value="RZQ/4", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="DQ_ODT_CS1", value="Disable", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="DQ_VREF_RANGE0", value="20.000", value_type="float") - et.SubElement(cs_memory,"efxpt:param", name="DQ_VREF_RANGE1", value="27.200", value_type="float") - et.SubElement(cs_memory,"efxpt:param", name="MEM_CA_RANGE", value="RANGE[1]", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="MEM_DQ_RANGE", value="RANGE[1]", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="NWR", value="nWR=6", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTD_CA_CS0", value="Obeys ODT_CA Bond Pad", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTD_CA_CS1", value="Obeys ODT_CA Bond Pad", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTE_CK_CS0", value="Override Disabled" ,value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTE_CK_CS1", value="Override Disabled" ,value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTE_CS_CS0", value="Override Disabled" ,value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="ODTE_CS_CS1", value="Override Disabled" ,value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="PDDS_CS0", value="RZQ/6", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="PDDS_CS1", value="RFU", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_READ", value="Yes", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_READ_DISABLED", value="RL=6,nRTP=8", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_READ_ENABLED", value="RL=6,nRTP=8", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_WRITE", value="Yes", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="WL_SET", value="Set A" ,value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="WL_SET_A", value="WL=4", value_type="str") - et.SubElement(cs_memory,"efxpt:param", name="WL_SET_B", value="WL=4", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="BLEN", value="BL=16 Sequential", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="CA_ODT_CS0", value="RZQ/4", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="CA_ODT_CS1", value="Disable", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="CA_VREF_RANGE0", value="27.200", value_type="float") + et.SubElement(cs_memory,"efxpt:param", name="CA_VREF_RANGE1", value="22.000", value_type="float") + et.SubElement(cs_memory,"efxpt:param", name="DQ_ODT_CS0", value="RZQ/4", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="DQ_ODT_CS1", value="Disable", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="DQ_VREF_RANGE0", value="20.000", value_type="float") + et.SubElement(cs_memory,"efxpt:param", name="DQ_VREF_RANGE1", value="27.200", value_type="float") + et.SubElement(cs_memory,"efxpt:param", name="MEM_CA_RANGE", value="RANGE[1]", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="MEM_DQ_RANGE", value="RANGE[1]", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="NWR", value="nWR=6", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="ODTD_CA_CS0", value="Obeys ODT_CA Bond Pad", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="ODTD_CA_CS1", value="Obeys ODT_CA Bond Pad", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="ODTE_CK_CS0", value="Override Disabled", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="ODTE_CK_CS1", value="Override Disabled", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="ODTE_CS_CS0", value="Override Disabled", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="ODTE_CS_CS1", value="Override Disabled", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="PDDS_CS0", value="RZQ/6", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="PDDS_CS1", value="RFU", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_READ", value="Yes", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_READ_DISABLED", value="RL=6,nRTP=8", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_READ_ENABLED", value="RL=6,nRTP=8", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="RL_DBI_WRITE", value="Yes", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="WL_SET", value="Set A", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="WL_SET_A", value="WL=4", value_type="str") + et.SubElement(cs_memory,"efxpt:param", name="WL_SET_B", value="WL=4", value_type="str") cs_memory_timing = et.SubElement(ddr, "efxpt:cs_memory_timing") - et.SubElement(cs_memory_timing,"efxpt:param", name="tCCD", value="8", value_type="int") - et.SubElement(cs_memory_timing,"efxpt:param", name="tCCDMW", value="32", value_type="int") - et.SubElement(cs_memory_timing,"efxpt:param", name="tFAW", value="40.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tPPD", value="4", value_type="int") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRAS", value="42.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRCD", value="18.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRPab", value="21.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRPpb", value="18.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRRD", value="10.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tRTP", value="7.500", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tSR", value="15.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tWR", value="18.000", value_type="float") - et.SubElement(cs_memory_timing,"efxpt:param", name="tWTR", value="10.000", value_type="float") + et.SubElement(cs_memory_timing,"efxpt:param", name="tCCD", value="8", value_type="int") + et.SubElement(cs_memory_timing,"efxpt:param", name="tCCDMW", value="32", value_type="int") + et.SubElement(cs_memory_timing,"efxpt:param", name="tFAW", value="40.000", value_type="float") + et.SubElement(cs_memory_timing,"efxpt:param", name="tPPD", value="4", value_type="int") + et.SubElement(cs_memory_timing,"efxpt:param", name="tRAS", value="42.000", value_type="float") + et.SubElement(cs_memory_timing,"efxpt:param", name="tRCD", value="18.000", value_type="float") + et.SubElement(cs_memory_timing,"efxpt:param", name="tRPab", value="21.000", value_type="float") + et.SubElement(cs_memory_timing,"efxpt:param", name="tRPpb", value="18.000", value_type="float") + et.SubElement(cs_memory_timing,"efxpt:param", name="tRRD", value="10.000", value_type="float") + et.SubElement(cs_memory_timing,"efxpt:param", name="tRTP", value="7.500", value_type="float") + et.SubElement(cs_memory_timing,"efxpt:param", name="tSR", value="15.000", value_type="float") + et.SubElement(cs_memory_timing,"efxpt:param", name="tWR", value="18.000", value_type="float") + et.SubElement(cs_memory_timing,"efxpt:param", name="tWTR", value="10.000", value_type="float") pin_swap = et.SubElement(ddr, "efxpt:pin_swap") - et.SubElement(pin_swap,"efxpt:param", name="CA[0]", value="CA[0]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="CA[1]", value="CA[1]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="CA[2]", value="CA[2]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="CA[3]", value="CA[3]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="CA[4]", value="CA[4]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="CA[5]", value="CA[5]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DM[0]", value="DM[0]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DM[1]", value="DM[1]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DM[2]", value="DM[2]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DM[3]", value="DM[3]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[0]", value="DQ[3]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="CA[0]", value="CA[0]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="CA[1]", value="CA[1]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="CA[2]", value="CA[2]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="CA[3]", value="CA[3]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="CA[4]", value="CA[4]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="CA[5]", value="CA[5]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DM[0]", value="DM[0]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DM[1]", value="DM[1]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DM[2]", value="DM[2]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DM[3]", value="DM[3]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[0]", value="DQ[3]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[10]", value="DQ[12]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[11]", value="DQ[11]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[12]", value="DQ[8]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[12]", value="DQ[8]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[13]", value="DQ[10]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[14]", value="DQ[13]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[15]", value="DQ[14]", value_type="str") @@ -474,7 +474,7 @@ class BaseSoC(SoCCore): et.SubElement(pin_swap,"efxpt:param", name="DQ[17]", value="DQ[17]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[18]", value="DQ[18]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[19]", value="DQ[19]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[1]", value="DQ[6]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[1]", value="DQ[6]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[20]", value="DQ[16]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[21]", value="DQ[20]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[22]", value="DQ[21]", value_type="str") @@ -485,16 +485,16 @@ class BaseSoC(SoCCore): et.SubElement(pin_swap,"efxpt:param", name="DQ[27]", value="DQ[30]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[28]", value="DQ[25]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[29]", value="DQ[27]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[2]", value="DQ[4]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[2]", value="DQ[4]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[30]", value="DQ[26]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="DQ[31]", value="DQ[24]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[3]", value="DQ[5]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[4]", value="DQ[0]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[5]", value="DQ[1]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[6]", value="DQ[7]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[7]", value="DQ[2]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[8]", value="DQ[15]", value_type="str") - et.SubElement(pin_swap,"efxpt:param", name="DQ[9]", value="DQ[9]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[3]", value="DQ[5]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[4]", value="DQ[0]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[5]", value="DQ[1]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[6]", value="DQ[7]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[7]", value="DQ[2]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[8]", value="DQ[15]", value_type="str") + et.SubElement(pin_swap,"efxpt:param", name="DQ[9]", value="DQ[9]", value_type="str") et.SubElement(pin_swap,"efxpt:param", name="ENABLE_PIN_SWAP", value="true", value_type="bool") platform.toolchain.ifacewriter.xml_blocks.append(DRAMXMLBlock()) @@ -502,18 +502,18 @@ class BaseSoC(SoCCore): # DRAM AXI-Ports. # -------------- ios = [(f"ddr0", 0, - Subsignal("ar_valid", Pins(1)), - Subsignal("ar_ready", Pins(1)), + Subsignal("ar_valid", Pins(1)), + Subsignal("ar_ready", Pins(1)), Subsignal("ar_addr", Pins(33)), Subsignal("ar_id", Pins(6)), Subsignal("ar_len", Pins(8)), Subsignal("ar_size", Pins(3)), Subsignal("ar_burst", Pins(2)), Subsignal("ar_lock", Pins(1)), - Subsignal("ar_apcmd", Pins(1)), + Subsignal("ar_apcmd", Pins(1)), Subsignal("ar_qos", Pins(1)), - Subsignal("aw_valid", Pins(1)), - Subsignal("aw_ready", Pins(1)), + Subsignal("aw_valid", Pins(1)), + Subsignal("aw_ready", Pins(1)), Subsignal("aw_addr", Pins(33)), Subsignal("aw_id", Pins(6)), Subsignal("aw_len", Pins(8)), @@ -523,19 +523,19 @@ class BaseSoC(SoCCore): Subsignal("aw_cache", Pins(4)), Subsignal("aw_qos", Pins(1)), Subsignal("aw_allstrb", Pins(1)), - Subsignal("aw_apcmd", Pins(1)), - Subsignal("awcobuf", Pins(1)), - Subsignal("w_valid", Pins(1)), - Subsignal("w_ready", Pins(1)), + Subsignal("aw_apcmd", Pins(1)), + Subsignal("awcobuf", Pins(1)), + Subsignal("w_valid", Pins(1)), + Subsignal("w_ready", Pins(1)), Subsignal("w_data", Pins(data_width)), Subsignal("w_strb", Pins(data_width//8)), Subsignal("w_last", Pins(1)), - Subsignal("b_valid", Pins(1)), - Subsignal("b_ready", Pins(1)), + Subsignal("b_valid", Pins(1)), + Subsignal("b_ready", Pins(1)), Subsignal("b_resp", Pins(1)), Subsignal("b_id", Pins(6)), - Subsignal("r_valid", Pins(1)), - Subsignal("r_ready", Pins(1)), + Subsignal("r_valid", Pins(1)), + Subsignal("r_ready", Pins(1)), Subsignal("r_data", Pins(data_width)), Subsignal("r_id", Pins(6)), Subsignal("r_resp", Pins(2)), @@ -595,9 +595,9 @@ class BaseSoC(SoCCore): cfgs = [(f"cfg", 0, Subsignal("start", Pins(1)), - Subsignal("reset", Pins(1)), + Subsignal("reset", Pins(1)), Subsignal("sel", Pins(1)), - Subsignal("done", Pins(1)), + Subsignal("done", Pins(1)), )] cfg = platform.add_iface_ios(cfgs) @@ -613,11 +613,11 @@ class BaseSoC(SoCCore): self.sync += self.cfg_count.eq(self.cfg_count + (self.cfg_count != 0xFF)) self.sync += self.cfg_state.eq(self.cfg_state | (self.cfg_count == 0xFF)) - # Use DRAM's target0 port as Main Ram ----------------------------------------------------- + # Use DRAM's target0 port as Main Ram. self.bus.add_region("main_ram", SoCRegion( origin = 0x4000_0000, size = 0x4000_0000, # 1GB. - mode="rwx", + mode ="rwx", )) # Build -------------------------------------------------------------------------------------------- @@ -625,9 +625,9 @@ class BaseSoC(SoCCore): def main(): from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=efinix_ti375_c529_dev_kit.Platform, description="LiteX SoC on Efinix Ti375 C529 Dev Kit.") - parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") - parser.add_target_argument("--cpu-clk-freq", default=100e6, type=float, help="System clock frequency.") - parser.add_target_argument("--with-ohci", action="store_true", help="Enable USB OHCI.") + parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") + parser.add_target_argument("--cpu-clk-freq", default=100e6, type=float, help="System clock frequency.") + parser.add_target_argument("--with-ohci", action="store_true", help="Enable USB OHCI.") sdopts = parser.target_group.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") @@ -636,7 +636,7 @@ def main(): soc = BaseSoC( sys_clk_freq = args.sys_clk_freq, cpu_clk_freq = args.cpu_clk_freq, - with_ohci = args.with_ohci, + with_ohci = args.with_ohci, **parser.soc_argdict) if args.with_spi_sdcard: soc.add_spi_sdcard()