diff --git a/CONTRIBUTORS b/CONTRIBUTORS index 23b75e5..2f12af4 100644 --- a/CONTRIBUTORS +++ b/CONTRIBUTORS @@ -85,3 +85,4 @@ Copyright (c) 2020 Vamsi K Vytla Copyright (c) 2021 Vegard Storheil Eriksen Copyright (c) 2020 YanekJ Copyright (c) 2021 Yoshimasa Niwa +Copyright (c) 2021 Alex Petrov diff --git a/README.md b/README.md index 9461471..66a77ce 100644 --- a/README.md +++ b/README.md @@ -199,6 +199,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try! ├── trenz_te0725 ├── trenz_tec0117 ├── tul_pynq_z2 + ├── u420t ├── xilinx_ac701 ├── xilinx_alveo_u250 ├── xilinx_alveo_u280 diff --git a/litex_boards/platforms/u420t.py b/litex_boards/platforms/u420t.py index b36ad1f..0578edc 100644 --- a/litex_boards/platforms/u420t.py +++ b/litex_boards/platforms/u420t.py @@ -4,7 +4,7 @@ # Copyright (c) 2018-2019 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause # Kintex7-420T -# Part xc7k420tiffg901-2L +# Part xc7k420tiffg901-2L v0.2 update # ported by Alex Petrov aka sysman from litex.build.generic_platform import * @@ -47,20 +47,52 @@ _io = [ IOStandard("LVCMOS33") ), - # SPIFlash (Micron N25Q256A / mt25ql256 (32MB)) - #("spiflash4x", 0, - # Subsignal("cs_n", Pins("V26")), + # SPIFlash (Micron N25Q256A (32MB)) + ("spiflash", 0, + Subsignal("cs_n", Pins("V26"), IOStandard("LVCMOS33")), + #Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), + Subsignal("mosi", Pins("R30"), IOStandard("LVCMOS33")), + Subsignal("miso", Pins("T30"), IOStandard("LVCMOS33")), + Subsignal("wp", Pins("R28"), IOStandard("LVCMOS33")), + Subsignal("hold", Pins("T28"), IOStandard("LVCMOS33")) + ), + ("spiflash4x", 0, + Subsignal("cs_n", Pins("V26"), IOStandard("LVCMOS33")), #Subsignal("clk", Pins("")), # driven through JTAG H13 #T22 ? - # Subsignal("dq", Pins("R30","T30","R28","T28")), - # IOStandard("LVCMOS33"), - #), - + Subsignal("dq", Pins("R30 T30 R28 T28"), IOStandard("LVCMOS33")) + ), ] # Connectors --------------------------------------------------------------------------------------- -# to add connector -_connectors = [] +# to add connector +_connectors = [ +# main board connector, pins as marked +( "main", { + # usb- 1 2 usb+ not used U3 usb3320 don't use + # GND 3 4 GND + # QSPI_CS 5 6 QSPI_D1 + # QSPI_D0 7 8 QSPI_CLK + 9: "B29", + # 10: "Program_B" key3 reset button + 11: "A28", + 12: "B27", + 13: "A27", + 14: "A26", + 15: "B25", + 16: "A25", + 17: "B24", + 18: "B23", + 19: "A23", + 20: "B22", + 21: "A22", + 22: "A21", + 23: "B20", + 24: "A20", + # 25,26,27,28: GND + # 29,30,31,32: V12 + }) +] # PMODS -------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/u420t.py b/litex_boards/targets/u420t.py index e72ffda..a8ecef1 100755 --- a/litex_boards/targets/u420t.py +++ b/litex_boards/targets/u420t.py @@ -6,15 +6,15 @@ # Copyright (c) 2020-2021 Xuanyu Hu # SPDX-License-Identifier: BSD-2-Clause # ported by Alex Petrov aka sysman -# Kintex7-420T -# Part xc7k420tiffg901-2L +# Kintex7-420T aliexpress +# Part xc7k420tiffg901-2L v0.2 from migen import * from litex_boards.platforms import u420t from litex.soc.interconnect import wishbone from litex.soc.cores.clock import * -#from litex.soc.integration.soc import SoCRegion +from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -28,14 +28,10 @@ class _CRG(Module): self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_idelay = ClockDomain() - # # # - #clk100 = platform.request("clk100") - # board is grade 2, but to fix halts use -1 self.submodules.pll = pll = S7MMCM(speedgrade=-2) ##self.submodules.pll = pll = S7MMCM(speedgrade=-1) - #self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst) - self.comb += pll.reset.eq(platform.request("user_btn_k3") | self.rst) + self.comb += pll.reset.eq(~platform.request("user_btn_k3") | self.rst) pll.register_clkin(platform.request("clk100"), 100e6) #workaround to bypass for clk100 error: No nets matched 'clk100' #line:940 litex/litex/build/xilinx/vivado.py " [get_ports {clk}]", clk=clk) @@ -52,13 +48,14 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_spi_flash=False, **kwargs): platform = u420t.Platform() # --- add more sram for riscv comfort + # xc7k420t BRAMs: 1670 (col length: RAMB18 160 RAMB36 80) kwargs["integrated_rom_size"] = 0x8000 # 8kb kwargs["integrated_sram_size"] = 0x10000 # 64kb - kwargs["integrated_main_ram_size"] = 0x20000 # 128kb + kwargs["integrated_main_ram_size"] = 0x40000 # 256kb ## change if needed # SoCCore ----------------------------------_----------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, @@ -72,10 +69,10 @@ class BaseSoC(SoCCore): # no video # no ram # SPI Flash -------------------------------------------------------------------------------- - #if with_spi_flash: - # from litespi.modules import W25Q256 - # from litespi.opcodes import SpiNorFlashOpCodes as Codes - # self.add_spi_flash(mode="1x", module=W25Q256(Codes.READ_1_1_1)) + if with_spi_flash: + from litespi.modules import N25Q256 + from litespi.opcodes import SpiNorFlashOpCodes as Codes + self.add_spi_flash(mode="4x", module=W25Q256(Codes.READ_1_1_4)) # Leds ------------------------------------------------------------------------------------- @@ -102,14 +99,13 @@ def main(): target_group.add_argument("--load", action="store_true", help="Load bitstream.") target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") # sdopts = target_group.add_mutually_exclusive_group() -# sdopts.add_argument("--with-spi-flash", action="store_true", help="Enable SPI-mode flash support.") + sdopts.add_argument("--with-spi-flash", action="store_true", help="Enable SPI-mode flash support.") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), -# with_video_terminal = args.with_video_terminal, **soc_core_argdict(args) ) # soc.platform.add_extension(u420t._sdcard_pmod_io)