From 1e1bec10c4e1ea78c328bac5f0660c536e71a019 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 25 Jan 2021 11:52:59 +0100
Subject: [PATCH] orangecrab: remove dm_remapping workaround: we are now using
 Wihsbone/L2 path with VexRiscv-SMP on this board.

---
 litex_boards/targets/orangecrab.py | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py
index 6a13a22..49c5b86 100755
--- a/litex_boards/targets/orangecrab.py
+++ b/litex_boards/targets/orangecrab.py
@@ -183,8 +183,7 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = ECP5DDRPHY(
                 pads         = ddram_pads,
                 sys_clk_freq = sys_clk_freq,
-                cmd_delay    = 0 if sys_clk_freq > 64e6 else 100,
-                dm_remapping = {0:1, 1:0})
+                cmd_delay    = 0 if sys_clk_freq > 64e6 else 100)
             self.ddrphy.settings.rtt_nom = "disabled"
             self.add_csr("ddrphy")
             if hasattr(ddram_pads, "vccio"):