diff --git a/litex_boards/platforms/gsd_butterstick.py b/litex_boards/platforms/gsd_butterstick.py index 8564147..9550eb0 100644 --- a/litex_boards/platforms/gsd_butterstick.py +++ b/litex_boards/platforms/gsd_butterstick.py @@ -28,6 +28,27 @@ _io_r1_0 = [ # Buttons ("user_btn", 0, Pins("U16"), IOStandard("SSTL135_I")), ("user_btn", 1, Pins("T17"), IOStandard("SSTL135_I")), + + + # RGMII Ethernet + ("eth_clocks", 0, + Subsignal("tx", Pins("E15")), + Subsignal("rx", Pins("D11")), + IOStandard("LVCMOS33"), + Misc("SLEWRATE=FAST"), + ), + + ("eth", 0, + Subsignal("rst_n", Pins("B20")), + Subsignal("mdio", Pins("D16")), + Subsignal("mdc", Pins("A19")), + Subsignal("rx_data", Pins("A16 C17 B17 A17")), + Subsignal("tx_ctl", Pins("D15")), + Subsignal("rx_ctl", Pins("B18")), + Subsignal("tx_data", Pins("C15 B16 A18 B19")), + IOStandard("LVCMOS33"), + Misc("SLEWRATE=FAST") + ), ] # Connectors --------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/gsd_butterstick.py b/litex_boards/targets/gsd_butterstick.py index cf56be0..aecfb7d 100755 --- a/litex_boards/targets/gsd_butterstick.py +++ b/litex_boards/targets/gsd_butterstick.py @@ -7,6 +7,11 @@ # Copyright (c) 2021 Greg Davill # SPDX-License-Identifier: BSD-2-Clause +# Build/Use: +# ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load +# litex_server --udp +# litex_term bridge + import os import sys import argparse @@ -21,6 +26,8 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser +from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII + # CRG --------------------------------------------------------------------------------------------- class _CRG(Module): @@ -51,7 +58,10 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, revision="1.0", device="25F", sys_clk_freq=int(60e6), toolchain="trellis", with_led_chaser=True, **kwargs): + def __init__(self, revision="1.0", device="25F", sys_clk_freq=int(60e6), toolchain="trellis", + with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, + with_led_chaser=True, + **kwargs) : platform = butterstick.Platform(revision=revision, device=device ,toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- @@ -63,6 +73,16 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) + # Ethernet / Etherbone --------------------------------------------------------------------- + if with_ethernet or with_etherbone: + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + if with_ethernet: + self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) + if with_etherbone: + self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) + # Leds ------------------------------------------------------------------------------------- if with_led_chaser: self.comb += platform.request("user_led_color").eq(0b010) # Blue. @@ -75,22 +95,33 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ButterStick") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--toolchain", default="trellis", help="FPGA use, trellis (default) or diamond") - parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)") - parser.add_argument("--revision", default="1.0", help="Board Revision: 1.0 (default)") - parser.add_argument("--device", default="85F", help="ECP5 device (default: 85F)") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--toolchain", default="trellis", help="FPGA use, trellis (default) or diamond") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") + parser.add_argument("--revision", default="1.0", help="Board Revision: 1.0 (default)") + parser.add_argument("--device", default="85F", help="ECP5 device (default: 85F)") + ethopts = parser.add_mutually_exclusive_group() + ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet") + ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone") + parser.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address") + parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting") builder_args(parser) soc_core_args(parser) trellis_args(parser) args = parser.parse_args() + assert not (args.with_etherbone and args.eth_dynamic_ip) + soc = BaseSoC( - toolchain = args.toolchain, - revision = args.revision, - device = args.device, - sys_clk_freq = int(float(args.sys_clk_freq)), + toolchain = args.toolchain, + revision = args.revision, + device = args.device, + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, + eth_ip = args.eth_ip, + eth_dynamic_ip = args.eth_dynamic_ip, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}