From 1f32dcf662ab41fc66a0d6e5ddf80d9dc870db44 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 30 Dec 2019 12:06:33 +0100 Subject: [PATCH] partner: rename orange_crab to orangecrab --- .../partner/platforms/{orange_crab.py => orangecrab.py} | 0 .../partner/targets/{orange_crab.py => orangecrab.py} | 4 ++-- 2 files changed, 2 insertions(+), 2 deletions(-) rename litex_boards/partner/platforms/{orange_crab.py => orangecrab.py} (100%) rename litex_boards/partner/targets/{orange_crab.py => orangecrab.py} (97%) diff --git a/litex_boards/partner/platforms/orange_crab.py b/litex_boards/partner/platforms/orangecrab.py similarity index 100% rename from litex_boards/partner/platforms/orange_crab.py rename to litex_boards/partner/platforms/orangecrab.py diff --git a/litex_boards/partner/targets/orange_crab.py b/litex_boards/partner/targets/orangecrab.py similarity index 97% rename from litex_boards/partner/targets/orange_crab.py rename to litex_boards/partner/targets/orangecrab.py index 5e9ea0f..fc7043c 100755 --- a/litex_boards/partner/targets/orange_crab.py +++ b/litex_boards/partner/targets/orangecrab.py @@ -8,7 +8,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import orange_crab +from litex_boards.platforms import orangecrab from litex.build.lattice.trellis import trellis_args, trellis_argdict @@ -76,7 +76,7 @@ class _CRG(Module): class BaseSoC(SoCSDRAM): def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs): - platform = orange_crab.Platform(toolchain=toolchain) + platform = orangecrab.Platform(toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,