From 1f6e7f36a589c0d53cd39156177d3c9d27cbad8b Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Fri, 28 Apr 2023 16:56:37 -0400 Subject: [PATCH] target/stlv7325-v2: fix typo in eth phy delay --- litex_boards/targets/sitlinv_stlv7325_v2.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/sitlinv_stlv7325_v2.py b/litex_boards/targets/sitlinv_stlv7325_v2.py index a872c46..6e5858c 100755 --- a/litex_boards/targets/sitlinv_stlv7325_v2.py +++ b/litex_boards/targets/sitlinv_stlv7325_v2.py @@ -112,8 +112,8 @@ class BaseSoC(SoCCore): self.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks", 0), pads = self.platform.request("eth", 0), - tx_delay = 1.48-9, - rx_delay = 1.48-9, + tx_delay = 1.48e-9, + rx_delay = 1.48e-9, ) self.add_ethernet(phy=self.ethphy)