diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py
index 470240f..d959e7e 100755
--- a/litex_boards/targets/orangecrab.py
+++ b/litex_boards/targets/orangecrab.py
@@ -60,12 +60,12 @@ class _CRG(Module):
             self.clock_domains.cd_usb_48 = ClockDomain()
             usb_pll = ECP5PLL()
             self.submodules += usb_pll
-            self.comb += usb_pll.reset.eq(~por_done | ~rst_n | self.rst)
+            self.comb += usb_pll.reset.eq(~por_done)
             usb_pll.register_clkin(clk48, 48e6)
             usb_pll.create_clkout(self.cd_usb_48, 48e6)
             usb_pll.create_clkout(self.cd_usb_12, 12e6)
 
-        # FPGA Reset (press usr_btn for 1 second to fallback to bootlooader)
+        # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
         reset_timer = WaitTimer(sys_clk_freq)
         self.submodules += reset_timer
         self.comb += reset_timer.wait.eq(~rst_n)
@@ -130,12 +130,12 @@ class _CRGSDRAM(Module):
             self.clock_domains.cd_usb_48 = ClockDomain()
             usb_pll = ECP5PLL()
             self.submodules += usb_pll
-            self.comb += usb_pll.reset.eq(~por_done | ~rst_n)
+            self.comb += usb_pll.reset.eq(~por_done)
             usb_pll.register_clkin(clk48, 48e6)
             usb_pll.create_clkout(self.cd_usb_48, 48e6)
             usb_pll.create_clkout(self.cd_usb_12, 12e6)
 
-        # FPGA Reset (press usr_btn for 1 second to fallback to bootlooader)
+        # FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
         reset_timer = WaitTimer(sys_clk_freq)
         self.submodules += reset_timer
         self.comb += reset_timer.wait.eq(~rst_n)