From 1fb24d4c71c9923c8e41fc5d6463a53d4fef5fe0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 4 Jan 2021 09:04:54 +0100 Subject: [PATCH] orangecrab: Avoid usb clock domain reset on usr_btn press or SoC reset. Allows the USB-ACM link to stay up during reset. --- litex_boards/targets/orangecrab.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 470240f..d959e7e 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -60,12 +60,12 @@ class _CRG(Module): self.clock_domains.cd_usb_48 = ClockDomain() usb_pll = ECP5PLL() self.submodules += usb_pll - self.comb += usb_pll.reset.eq(~por_done | ~rst_n | self.rst) + self.comb += usb_pll.reset.eq(~por_done) usb_pll.register_clkin(clk48, 48e6) usb_pll.create_clkout(self.cd_usb_48, 48e6) usb_pll.create_clkout(self.cd_usb_12, 12e6) - # FPGA Reset (press usr_btn for 1 second to fallback to bootlooader) + # FPGA Reset (press usr_btn for 1 second to fallback to bootloader) reset_timer = WaitTimer(sys_clk_freq) self.submodules += reset_timer self.comb += reset_timer.wait.eq(~rst_n) @@ -130,12 +130,12 @@ class _CRGSDRAM(Module): self.clock_domains.cd_usb_48 = ClockDomain() usb_pll = ECP5PLL() self.submodules += usb_pll - self.comb += usb_pll.reset.eq(~por_done | ~rst_n) + self.comb += usb_pll.reset.eq(~por_done) usb_pll.register_clkin(clk48, 48e6) usb_pll.create_clkout(self.cd_usb_48, 48e6) usb_pll.create_clkout(self.cd_usb_12, 12e6) - # FPGA Reset (press usr_btn for 1 second to fallback to bootlooader) + # FPGA Reset (press usr_btn for 1 second to fallback to bootloader) reset_timer = WaitTimer(sys_clk_freq) self.submodules += reset_timer self.comb += reset_timer.wait.eq(~rst_n)