diff --git a/litex_boards/platforms/crosslink_nx_vip.py b/litex_boards/platforms/crosslink_nx_vip.py
index bbcb42e..b492511 100644
--- a/litex_boards/platforms/crosslink_nx_vip.py
+++ b/litex_boards/platforms/crosslink_nx_vip.py
@@ -92,6 +92,26 @@ _io = [
         Subsignal("cam_frame_sync", Pins("U1")),
     ),
 
+    # HyperRAM
+    ("hyperram", 0,
+        Subsignal("dq", Pins("Y6 W7 V7 P7 P8 R8 T8 Y7"), IOStandard("LVCMOS18H")),
+        Subsignal("rwds", Pins("W6"), IOStandard("LVCMOS18H")),
+        Subsignal("cs_n", Pins("V6"), IOStandard("LVCMOS18H")),
+        Subsignal("rst_n", Pins("U7"), IOStandard("LVCMOS18H")),
+        Subsignal("clk", Pins("R7"), IOStandard("LVDS")),
+        # Subsignal("clk_n", Pins("T7"), IOStandard("LVDS")),
+        Misc("SLEWRATE=FAST")
+    ),
+    ("hyperram", 1,
+        Subsignal("dq", Pins("W8 V9 W9 Y9 T10 T11 U10 V10"), IOStandard("LVCMOS18H")),
+        Subsignal("rwds", Pins("R10"), IOStandard("LVCMOS18H")),
+        Subsignal("cs_n", Pins("P9"), IOStandard("LVCMOS18H")),
+        Subsignal("rst_n", Pins("P10"), IOStandard("LVCMOS18H")),
+        Subsignal("clk", Pins("W10"), IOStandard("LVDS")),
+        # Subsignal("clk_n", Pins("Y10"), IOStandard("LVDS")),
+        Misc("SLEWRATE=FAST")
+    ),
+
     # MIPI camera modules
     # Note that use of MIPI_DPHY standard for + and LVCMOS12H for - is copied from Lattice PDC
     ("camera", 0,
diff --git a/litex_boards/targets/crosslink_nx_vip.py b/litex_boards/targets/crosslink_nx_vip.py
index 9c503e5..299f000 100644
--- a/litex_boards/targets/crosslink_nx_vip.py
+++ b/litex_boards/targets/crosslink_nx_vip.py
@@ -17,6 +17,10 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex_boards.platforms import crosslink_nx_vip
 
+from litex_boards.platforms import crosslink_nx_vip
+
+from litehyperbus.core.hyperbus import HyperRAM
+
 from litex.soc.cores.nxlram import NXLRAM
 from litex.soc.cores.spi_flash import SpiFlash
 from litex.build.io import CRG
@@ -62,7 +66,7 @@ class BaseSoC(SoCCore):
         "sram":             0x40000000,
         "csr":              0xf0000000,
     }
-    def __init__(self, sys_clk_freq, **kwargs):
+    def __init__(self, sys_clk_freq, hyperram="none", **kwargs):
         platform = crosslink_nx_vip.Platform()
 
         platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
@@ -79,10 +83,17 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
-        # 128KB LRAM (used as SRAM) ---------------------------------------------------------------
-        size = 128*kB
-        self.submodules.spram = NXLRAM(32, size)
-        self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size)
+        if hyperram == "none":
+            # 128KB LRAM (used as SRAM) ------------------------------------------------------------
+            size = 128*kB
+            self.submodules.spram = NXLRAM(32, size)
+            self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size)
+        else:
+            # Use HyperRAM generic PHY as SRAM -----------------------------------------------------
+            size = 8*1024*kB
+            hr_pads = platform.request("hyperram", int(hyperram))
+            self.submodules.hyperram = HyperRAM(hr_pads)
+            self.register_mem("sram", self.mem_map["sram"], self.hyperram.bus, size)
 
         # Leds -------------------------------------------------------------------------------------
         self.submodules.leds = LedChaser(
@@ -94,16 +105,17 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board")
+    parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
     parser.add_argument("--load", action="store_true", help="Load bitstream")
+    parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip 0 or 1 (default=none)")
     parser.add_argument("--sys-clk-freq",  default=75e6, help="System clock frequency (default=75MHz)")
     parser.add_argument("--prog-target",  default="direct", help="Programming Target: direct or flash")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_core_argdict(args))
+    soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), hyperram=args.with_hyperram, **soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder_kargs = {}
     builder.build(**builder_kargs, run=args.build)