From 21207533b0ca6abd21e747dfd8b4c518318931a7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 4 Mar 2021 19:49:03 +0100 Subject: [PATCH] targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence). --- litex_boards/targets/alveo_u250.py | 2 +- litex_boards/targets/kcu105.py | 2 +- litex_boards/targets/mercury_xu5.py | 2 +- litex_boards/targets/vcu118.py | 2 +- litex_boards/targets/xcu1525.py | 2 +- litex_boards/targets/zcu104.py | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index 8bb72c9..daed9e0 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -43,7 +43,7 @@ class _CRG(Module): self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("clk300", 0), 300e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index 42d0a6a..8bd6a7b 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -45,7 +45,7 @@ class _CRG(Module): self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_idelay, 200e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_eth, 200e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index 378ab60..95624fb 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -39,7 +39,7 @@ class _CRG(Module): self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("clk100"), 100e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index ea90331..343aed4 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -40,7 +40,7 @@ class _CRG(Module): self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index 804c5a7..a200f22 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -42,7 +42,7 @@ class _CRG(Module): self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("clk300", ddram_channel), 300e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [ diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index 55ba03d..05b9ef8 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -41,7 +41,7 @@ class _CRG(Module): self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [