From 2129b677792a81a13d1bcd2cea327a9cdd4b96ce Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 5 May 2020 09:47:55 +0200 Subject: [PATCH] platforms: make sure all plarforms have separators. --- litex_boards/platforms/de10lite.py | 2 ++ litex_boards/platforms/de1soc.py | 4 ++-- litex_boards/platforms/de2_115.py | 4 ++-- litex_boards/platforms/nereid.py | 2 ++ litex_boards/platforms/sp605.py | 7 ++++++- litex_boards/platforms/trellisboard.py | 2 ++ 6 files changed, 16 insertions(+), 5 deletions(-) diff --git a/litex_boards/platforms/de10lite.py b/litex_boards/platforms/de10lite.py index 9712329..0904a84 100644 --- a/litex_boards/platforms/de10lite.py +++ b/litex_boards/platforms/de10lite.py @@ -5,6 +5,7 @@ from litex.build.generic_platform import * from litex.build.altera import AlteraPlatform from litex.build.altera.programmer import USBBlaster +# IOs ---------------------------------------------------------------------------------------------- _io = [ ("clk10", 0, Pins("N5"), IOStandard("3.3-V LVTTL")), @@ -103,6 +104,7 @@ _io = [ ) ] +# Platform ----------------------------------------------------------------------------------------- class Platform(AlteraPlatform): default_clk_name = "clk50" diff --git a/litex_boards/platforms/de1soc.py b/litex_boards/platforms/de1soc.py index 1cd42fd..3377ab9 100644 --- a/litex_boards/platforms/de1soc.py +++ b/litex_boards/platforms/de1soc.py @@ -5,7 +5,7 @@ from litex.build.generic_platform import * from litex.build.altera import AlteraPlatform from litex.build.altera.programmer import USBBlaster -# IOs ------------------------------------------------------------------ +# IOs ---------------------------------------------------------------------------------------------- _io = [ ("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")), @@ -34,7 +34,7 @@ _io = [ ), ] -# Platform ------------------------------------------------------------- +# Platform ----------------------------------------------------------------------------------------- class Platform(AlteraPlatform): default_clk_name = "clk50" diff --git a/litex_boards/platforms/de2_115.py b/litex_boards/platforms/de2_115.py index 6158d1c..d8cedba 100644 --- a/litex_boards/platforms/de2_115.py +++ b/litex_boards/platforms/de2_115.py @@ -5,7 +5,7 @@ from litex.build.generic_platform import * from litex.build.altera import AlteraPlatform from litex.build.altera.programmer import USBBlaster -# IOs ------------------------------------------------------------------ +# IOs ---------------------------------------------------------------------------------------------- _io = [ ("clk50", 0, Pins("Y2"), IOStandard("3.3-V LVTTL")), @@ -34,7 +34,7 @@ _io = [ ), ] -# Platform ------------------------------------------------------------- +# Platform ----------------------------------------------------------------------------------------- class Platform(AlteraPlatform): default_clk_name = "clk50" diff --git a/litex_boards/platforms/nereid.py b/litex_boards/platforms/nereid.py index 490aee8..5d913a9 100644 --- a/litex_boards/platforms/nereid.py +++ b/litex_boards/platforms/nereid.py @@ -165,6 +165,8 @@ _io = [ ), ] +# Connectors --------------------------------------------------------------------------------------- + _connectors = [ ("HPC", { diff --git a/litex_boards/platforms/sp605.py b/litex_boards/platforms/sp605.py index 1f3188d..624d891 100644 --- a/litex_boards/platforms/sp605.py +++ b/litex_boards/platforms/sp605.py @@ -1,11 +1,12 @@ # This file is Copyright (c) 2019 Michael Betz # License: BSD - from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform from litex.build.openocd import OpenOCD +# IOs ---------------------------------------------------------------------------------------------- + _io = [ ("user_led", 0, Pins("D17"), IOStandard("LVCMOS25")), ("user_led", 1, Pins("AB4"), IOStandard("LVCMOS25")), @@ -56,6 +57,8 @@ _io = [ ), ] +# Connectors --------------------------------------------------------------------------------------- + _connectors = [ ("LPC", { "DP0_C2M_P" : "B16", @@ -154,6 +157,8 @@ _connectors = [ }), ] +# Platform ----------------------------------------------------------------------------------------- + class Platform(XilinxPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 diff --git a/litex_boards/platforms/trellisboard.py b/litex_boards/platforms/trellisboard.py index e5dd386..5d5655f 100644 --- a/litex_boards/platforms/trellisboard.py +++ b/litex_boards/platforms/trellisboard.py @@ -198,6 +198,8 @@ _io = [ ), ] +# Connectors --------------------------------------------------------------------------------------- + _connectors = [ ("pmoda", "F19 F20 B22 C23 D14 A13 E22 D23"), ("pmodb", "C25 A26 F23 F25 B25 D25 F22 F24"),