diff --git a/litex_boards/partner/targets/fomu.py b/litex_boards/partner/targets/fomu.py
index 546c13b..6fa6eff 100755
--- a/litex_boards/partner/targets/fomu.py
+++ b/litex_boards/partner/targets/fomu.py
@@ -182,7 +182,7 @@ class BaseSoC(SoCCore):
         # Use this as CPU RAM.
         spram_size = 128*1024
         self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
-        self.register_mem("sram", 0x10000000, self.spram.bus, spram_size)
+        self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
 
         if usb_core is not None:
             # Add USB pads.  We use DummyUsb, which simply enumerates as a USB