From 2214c7baeca04480d6ee19fe78c029ba62cea811 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Fri, 20 May 2022 04:42:06 +0700 Subject: [PATCH] enclustra_mercury_kx2: remove useless clk100, because it is not connected to a clock pin --- litex_boards/platforms/enclustra_mercury_kx2.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/litex_boards/platforms/enclustra_mercury_kx2.py b/litex_boards/platforms/enclustra_mercury_kx2.py index 95db42d..caa8d0b 100644 --- a/litex_boards/platforms/enclustra_mercury_kx2.py +++ b/litex_boards/platforms/enclustra_mercury_kx2.py @@ -12,7 +12,6 @@ from litex.build.openocd import OpenOCD _io = [ # Clk / Rst - ("clk100", 0, Pins("AD24"), IOStandard("LVCMOS18")), ("clk200", 0, Subsignal("p", Pins("AB11"), IOStandard("LVDS")), Subsignal("n", Pins("AC11"), IOStandard("LVDS")) @@ -114,5 +113,4 @@ class Platform(XilinxPlatform): def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) - self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) - self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) + self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) \ No newline at end of file