From 2264df8a0a92267b0050d500d27549eb5f3e3e0b Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Mon, 5 Feb 2024 11:42:14 +0100 Subject: [PATCH] adi_adrv2crr_fmc: Speedgrade of the PLL is -2 Speedgrade of the chip was updated in a previous commit, but I forgot to update the PLL too Signed-off-by: Sylvain Munaut --- litex_boards/targets/adi_adrv2crr_fmc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/adi_adrv2crr_fmc.py b/litex_boards/targets/adi_adrv2crr_fmc.py index 5597c61..013cec0 100755 --- a/litex_boards/targets/adi_adrv2crr_fmc.py +++ b/litex_boards/targets/adi_adrv2crr_fmc.py @@ -41,7 +41,7 @@ class CRG(LiteXModule): # # # - self.pll = pll = USPMMCM(speedgrade=-1) + self.pll = pll = USPMMCM(speedgrade=-2) self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("ddram_refclk", ddram_channel), 300e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)