From 22bdb575d14814ee0dd60a56d5178a34c5502fe5 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Mon, 8 May 2023 16:24:15 +0700 Subject: [PATCH] reset is active high --- litex_boards/platforms/pcbarts_klusterlab.py | 2 +- litex_boards/targets/pcbarts_klusterlab.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/platforms/pcbarts_klusterlab.py b/litex_boards/platforms/pcbarts_klusterlab.py index c15d31e..4ecd9fe 100644 --- a/litex_boards/platforms/pcbarts_klusterlab.py +++ b/litex_boards/platforms/pcbarts_klusterlab.py @@ -31,7 +31,7 @@ _io = [ Subsignal("n", Pins("H5"), IOStandard("DIFF_HSTL_I_10")) ), - ("cpu_reset_n", 0, Pins("A20"), IOStandard("LVCMOS18")), + ("cpu_reset", 0, Pins("A20"), IOStandard("LVCMOS18")), ("pi_reset_n", 0, Pins("A18"), IOStandard("LVCMOS33")), # Leds diff --git a/litex_boards/targets/pcbarts_klusterlab.py b/litex_boards/targets/pcbarts_klusterlab.py index 31add9c..496a946 100755 --- a/litex_boards/targets/pcbarts_klusterlab.py +++ b/litex_boards/targets/pcbarts_klusterlab.py @@ -35,7 +35,7 @@ class _CRG(LiteXModule): # # # self.pll = pll = S7PLL(speedgrade=-2) - self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst) + self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst) pll.register_clkin(platform.request("clk200"), 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)