From 22f167dde4bf1ff0858f3d2a9c937c5498ec3b7f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 25 Mar 2021 18:19:20 +0100 Subject: [PATCH] targets/sqrl_acorn_cle_215: Add missing false path constraints. --- litex_boards/targets/sqrl_acorn_cle_215.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/litex_boards/targets/sqrl_acorn_cle_215.py b/litex_boards/targets/sqrl_acorn_cle_215.py index 48e77ab..83f6c20 100755 --- a/litex_boards/targets/sqrl_acorn_cle_215.py +++ b/litex_boards/targets/sqrl_acorn_cle_215.py @@ -107,6 +107,11 @@ class BaseSoC(SoCCore): data_width = 128, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) + # FIXME: Improve (Make it generic and apply it to all targets). + platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clkout0] -group [get_clocks userclk2] -asynchronous",) + platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clkout0] -group [get_clocks clk_125mhz] -asynchronous") + platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clkout0] -group [get_clocks clk_250mhz] -asynchronous") + platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clk_125mhz] -group [get_clocks clk_250mhz] -asynchronous") # SATA ------------------------------------------------------------------------------------- if with_sata: