From 22f18f618e4ba5f5610cd647db1bec6a987149a6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 26 May 2020 08:36:06 +0200 Subject: [PATCH] pano_logic_g2: move gmii_rst_n to _CRG. --- litex_boards/targets/pano_logic_g2.py | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py index 44f4a5b..d067ea1 100755 --- a/litex_boards/targets/pano_logic_g2.py +++ b/litex_boards/targets/pano_logic_g2.py @@ -24,6 +24,10 @@ class _CRG(Module): # # # + # Take Ethernet PHY out of reset to enable clk125 (25MHz otherwise). + gmii_rst_n = platform.request("gmii_rst_n") + self.comb += gmii_rst_n.eq(1) + self.submodules.pll = pll = S6PLL(speedgrade=-2) pll.register_clkin(platform.request("clk125"), 125e6) pll.create_clkout(self.cd_sys, clk_freq) @@ -46,12 +50,6 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq) self.add_csr("leds") - # Take Ethernet Phy out of reset for SYSCLK of 125 Mhz - gmii_rst_n = platform.request("gmii_rst_n") - self.comb += [ - gmii_rst_n.eq(1) - ] - # Build -------------------------------------------------------------------------------------------- def main():