From 23760e2eae5fa819d8076a5440bada1ec7cc8000 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 22 Jan 2021 22:55:02 +0100 Subject: [PATCH] orangecrab/CRGSDRAM: add missing rst signal (to reset from the SoC). --- litex_boards/targets/orangecrab.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index c777fdf..6a13a22 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -76,6 +76,7 @@ class _CRG(Module): class _CRGSDRAM(Module): def __init__(self, platform, sys_clk_freq, with_usb_pll=False): + self.rst = Signal() self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() @@ -102,7 +103,7 @@ class _CRGSDRAM(Module): # PLL sys2x_clk_ecsout = Signal() self.submodules.pll = pll = ECP5PLL() - self.comb += pll.reset.eq(~por_done | ~rst_n) + self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst) pll.register_clkin(clk48, 48e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_init, 24e6)