From 2392473b8976b9425a0eed9a13cf26e3cbc175f7 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 30 Mar 2024 11:54:28 +0100 Subject: [PATCH] targets/xilinx_zc706: typo ZCU -> ZC --- litex_boards/targets/xilinx_zc706.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/xilinx_zc706.py b/litex_boards/targets/xilinx_zc706.py index 08bbaa8..545dc99 100755 --- a/litex_boards/targets/xilinx_zc706.py +++ b/litex_boards/targets/xilinx_zc706.py @@ -100,7 +100,7 @@ class BaseSoC(SoCCore): self.crg = _CRG(platform, sys_clk_freq) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU706", **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZC706", **kwargs) # DDR3 SDRAM ------------------------------------------------------------------------------- #if not self.integrated_main_ram_size: