From 23b1b154862a502dda443ff0b6c208ebffdf62b4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 14 Apr 2022 12:13:03 +0200 Subject: [PATCH] Add initial/minimal Pluto SDR support. --- litex_boards/__init__.py | 1 + litex_boards/platforms/adi_plutosdr.py | 33 ++++++++ litex_boards/targets/adi_plutosdr.py | 105 +++++++++++++++++++++++++ 3 files changed, 139 insertions(+) create mode 100644 litex_boards/platforms/adi_plutosdr.py create mode 100755 litex_boards/targets/adi_plutosdr.py diff --git a/litex_boards/__init__.py b/litex_boards/__init__.py index d105cd1..69a8b55 100644 --- a/litex_boards/__init__.py +++ b/litex_boards/__init__.py @@ -7,6 +7,7 @@ import importlib vendors = [ "1bitsquared", + "adi", "alinx", "antmicro", "arduino", diff --git a/litex_boards/platforms/adi_plutosdr.py b/litex_boards/platforms/adi_plutosdr.py new file mode 100644 index 0000000..f9dddcf --- /dev/null +++ b/litex_boards/platforms/adi_plutosdr.py @@ -0,0 +1,33 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2022 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform, VivadoProgrammer + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # GPIOs + ("gpio", 0, Pins("K13"), IOStandard("LVCMOS18")), + ("gpio", 1, Pins("M12"), IOStandard("LVCMOS18")), + ("gpio", 2, Pins("R10"), IOStandard("LVCMOS18")), +] + +# Connectors --------------------------------------------------------------------------------------- + +_connectors = [] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + def __init__(self, toolchain="vivado"): + XilinxPlatform.__init__(self, "xc7z010clg225-1", _io, _connectors, toolchain=toolchain) + + def create_programmer(self): + return VivadoProgrammer() + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/targets/adi_plutosdr.py b/litex_boards/targets/adi_plutosdr.py new file mode 100755 index 0000000..f0db331 --- /dev/null +++ b/litex_boards/targets/adi_plutosdr.py @@ -0,0 +1,105 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2022 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +# Build/Use: +# ./adi_plutosdr.py --build --load +# litex_server --jtag --jtag-config=openocd_xc7_ft232.cfg +# litex_term crossover + +from migen import * + +from litex_boards.platforms import adi_plutosdr +from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict + +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * + +from litex.soc.cores.clock import * + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + + # # # + + # CFGM Clk ~65MHz. + cfgm_clk = Signal() + cfgm_clk_freq = int(65e6) + self.specials += Instance("STARTUPE2", + i_CLK = 0, + i_GSR = 0, + i_GTS = 0, + i_KEYCLEARB = 1, + i_PACK = 0, + i_USRCCLKO = cfgm_clk, + i_USRCCLKTS = 0, + i_USRDONEO = 1, + i_USRDONETS = 1, + o_CFGMCLK = cfgm_clk + ) + + # PLL + self.submodules.pll = pll = S7PLL(speedgrade=-1) + self.comb += pll.reset.eq(self.rst) + pll.register_clkin(cfgm_clk, cfgm_clk_freq) + pll.create_clkout(self.cd_sys, sys_clk_freq) + platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(100e6), **kwargs): + platform = adi_plutosdr.Platform() + + # SoCCore ---------------------------------------------------------------------------------- + kwargs["uart_name"] = "crossover" + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Pluto SDR", + **kwargs + ) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # JTAGBone --------------------------------------------------------------------------------- + self.add_jtagbone() + + # GPIOS ------------------------------------------------------------------------------------ + self.comb += platform.request("gpio", 0).eq(ClockSignal("sys")) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + from litex.soc.integration.soc import LiteXSoCArgumentParser + parser = LiteXSoCArgumentParser(description="LiteX SoC on Pluto SDR") + target_group = parser.add_argument_group(title="Target options") + target_group.add_argument("--build", action="store_true", help="Build bitstream.") + target_group.add_argument("--load", action="store_true", help="Load bitstream.") + target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") + + builder_args(parser) + soc_core_args(parser) + vivado_build_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_core_argdict(args) + ) + builder = Builder(soc, **builder_argdict(args)) + builder.build(**vivado_build_argdict(args), run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1) + +if __name__ == "__main__": + main()