From 24033e331c192a84dc906fbecadaca0e2729c8b9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 24 Mar 2020 19:59:42 +0100 Subject: [PATCH] targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support. --- litex_boards/targets/de0nano.py | 9 +++------ litex_boards/targets/de10lite.py | 7 +++---- litex_boards/targets/de10nano.py | 9 +++------ litex_boards/targets/de1soc.py | 9 +++------ litex_boards/targets/de2_115.py | 9 +++------ litex_boards/targets/hadbadge.py | 4 ++-- litex_boards/targets/linsn_rv901t.py | 13 +++++-------- litex_boards/targets/minispartan6.py | 16 ++++++---------- litex_boards/targets/ulx3s.py | 6 +++--- 9 files changed, 31 insertions(+), 51 deletions(-) diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index e3ca868..edc020d 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -22,7 +22,7 @@ from litedram.phy import GENSDRPHY class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # @@ -43,7 +43,7 @@ class _CRG(Module): p_CLK1_DIVIDE_BY = 1, p_CLK1_DUTY_CYCLE = 50, p_CLK1_MULTIPLY_BY = 1, - p_CLK1_PHASE_SHIFT = "-10000", + p_CLK1_PHASE_SHIFT = "5000", # 90° p_COMPENSATE_CLOCK = "CLK0", p_INCLK0_INPUT_FREQUENCY = 20000, p_OPERATION_MODE = "NORMAL", @@ -61,10 +61,7 @@ class _CRG(Module): self.cd_sys.clk.eq(pll_clk_out[0]), self.cd_sys_ps.clk.eq(pll_clk_out[1]), ] - self.specials += [ - AsyncResetSynchronizer(self.cd_sys, ~pll_locked), - AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked) - ] + self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_locked) # SDRAM clock self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index d7dbbe3..d613a03 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -24,7 +24,7 @@ from litevideo.terminal.core import Terminal class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) self.clock_domains.cd_vga = ClockDomain(reset_less=True) # # # @@ -46,7 +46,7 @@ class _CRG(Module): p_CLK1_DIVIDE_BY = 1, p_CLK1_DUTY_CYCLE = 50, p_CLK1_MULTIPLY_BY = 1, - p_CLK1_PHASE_SHIFT = "-10000", + p_CLK1_PHASE_SHIFT = "5000", # 90° p_CLK2_DIVIDE_BY = 2, p_CLK2_DUTY_CYCLE = 50, p_CLK2_MULTIPLY_BY = 1, @@ -70,8 +70,7 @@ class _CRG(Module): ] self.specials += [ AsyncResetSynchronizer(self.cd_sys, ~pll_locked), - AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked), - AsyncResetSynchronizer(self.cd_vga, ~pll_locked) + AsyncResetSynchronizer(self.cd_vga, ~pll_locked), ] # SDRAM clock diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index 5c3521f..db7bb24 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -22,7 +22,7 @@ from litedram.phy import GENSDRPHY class _CRG(Module): def __init__(self, platform, with_sdram=False): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # @@ -43,7 +43,7 @@ class _CRG(Module): p_CLK1_DIVIDE_BY = 1, p_CLK1_DUTY_CYCLE = 50, p_CLK1_MULTIPLY_BY = 1, - p_CLK1_PHASE_SHIFT = "-10000", + p_CLK1_PHASE_SHIFT = "5000", # 90° p_COMPENSATE_CLOCK = "CLK0", p_INCLK0_INPUT_FREQUENCY = 20000, p_OPERATION_MODE = "NORMAL", @@ -61,10 +61,7 @@ class _CRG(Module): self.cd_sys.clk.eq(pll_clk_out[0]), self.cd_sys_ps.clk.eq(pll_clk_out[1]), ] - self.specials += [ - AsyncResetSynchronizer(self.cd_sys, ~pll_locked), - AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked) - ] + self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_locked) if with_sdram: self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py index 61bdc52..f9c7869 100755 --- a/litex_boards/targets/de1soc.py +++ b/litex_boards/targets/de1soc.py @@ -22,7 +22,7 @@ from litedram.phy import GENSDRPHY class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # @@ -43,7 +43,7 @@ class _CRG(Module): p_CLK1_DIVIDE_BY = 1, p_CLK1_DUTY_CYCLE = 50, p_CLK1_MULTIPLY_BY = 1, - p_CLK1_PHASE_SHIFT = "-10000", + p_CLK1_PHASE_SHIFT = "5000", # 90° p_COMPENSATE_CLOCK = "CLK0", p_INCLK0_INPUT_FREQUENCY = 20000, p_OPERATION_MODE = "NORMAL", @@ -61,10 +61,7 @@ class _CRG(Module): self.cd_sys.clk.eq(pll_clk_out[0]), self.cd_sys_ps.clk.eq(pll_clk_out[1]), ] - self.specials += [ - AsyncResetSynchronizer(self.cd_sys, ~pll_locked), - AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked) - ] + self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_locked) # SDRAM clock self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) diff --git a/litex_boards/targets/de2_115.py b/litex_boards/targets/de2_115.py index 6b2e31d..754eeba 100755 --- a/litex_boards/targets/de2_115.py +++ b/litex_boards/targets/de2_115.py @@ -22,7 +22,7 @@ from litedram.phy import GENSDRPHY class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # @@ -43,7 +43,7 @@ class _CRG(Module): p_CLK1_DIVIDE_BY = 1, p_CLK1_DUTY_CYCLE = 50, p_CLK1_MULTIPLY_BY = 1, - p_CLK1_PHASE_SHIFT = "-10000", + p_CLK1_PHASE_SHIFT = "5000", # 90° p_COMPENSATE_CLOCK = "CLK0", p_INCLK0_INPUT_FREQUENCY = 20000, p_OPERATION_MODE = "NORMAL", @@ -61,10 +61,7 @@ class _CRG(Module): self.cd_sys.clk.eq(pll_clk_out[0]), self.cd_sys_ps.clk.eq(pll_clk_out[1]), ] - self.specials += [ - AsyncResetSynchronizer(self.cd_sys, ~pll_locked), - AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked) - ] + self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_locked) # SDRAM clock self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index d1fff8b..3d4ced2 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -41,8 +41,8 @@ class _CRG(Module): # PLL self.submodules.pll = pll = ECP5PLL() pll.register_clkin(clk8, 8e6) - pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11) - pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked) # SDRAM clock diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index 946f229..d7f26d3 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -6,6 +6,7 @@ import argparse from migen import * +from migen.genlib.io import DDROutput from litex_boards.platforms import linsn_rv901t @@ -35,14 +36,10 @@ class _CRG(Module): self.submodules.pll = pll = S6PLL(speedgrade=-2) pll.register_clkin(clk25, 25e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=270) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) - self.specials += Instance("ODDR2", - p_DDR_ALIGNMENT="NONE", - p_INIT=0, p_SRTYPE="SYNC", - i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1, - i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk, - o_Q=platform.request("sdram_clock")) + # SDRAM clock + self.specials += DDROutput(0, 1, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ @@ -59,7 +56,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cmd_latency=2) self.add_sdram("sdram", phy = self.sdrphy, module = M12L64322A(sys_clk_freq, "1:1"), diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py index 9fa596a..7ba64fa 100755 --- a/litex_boards/targets/minispartan6.py +++ b/litex_boards/targets/minispartan6.py @@ -9,6 +9,7 @@ import argparse from fractions import Fraction from migen import * +from migen.genlib.io import DDROutput from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import minispartan6 @@ -26,27 +27,22 @@ from litedram.phy import GENSDRPHY class _CRG(Module): def __init__(self, platform, clk_freq): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # self.submodules.pll = pll = S6PLL(speedgrade=-1) pll.register_clkin(platform.request("clk32"), 32e6) pll.create_clkout(self.cd_sys, clk_freq) - pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270) + pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90) - self.specials += Instance("ODDR2", - p_DDR_ALIGNMENT="NONE", - p_INIT=0, p_SRTYPE="SYNC", - i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1, - i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk, - o_Q=platform.request("sdram_clock")) + # SDRAM clock + self.specials += DDROutput(0, 1, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(80e6), **kwargs): - assert sys_clk_freq == int(80e6) platform = minispartan6.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -57,7 +53,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cmd_latency=2) self.add_sdram("sdram", phy = self.sdrphy, module = AS4C16M16(sys_clk_freq, "1:1"), diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index ce0ddcd..450ca94 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -40,8 +40,8 @@ class _CRG(Module): self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(rst) pll.register_clkin(clk25, 25e6) - pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11) - pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) # SDRAM clock @@ -66,7 +66,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1"),