diff --git a/litex_boards/platforms/fairwaves_xtrx.py b/litex_boards/platforms/fairwaves_xtrx.py
index fecb80c..8a36d1d 100644
--- a/litex_boards/platforms/fairwaves_xtrx.py
+++ b/litex_boards/platforms/fairwaves_xtrx.py
@@ -29,6 +29,80 @@ _io = [
         Subsignal("tx_p",  Pins("B6")),
         Subsignal("tx_n",  Pins("A6")),
     ),
+
+    # SPIFlash.
+    ("flash_cs_n", 0, Pins("K19"), IOStandard("LVCMOS25")),
+    ("flash", 0,
+        Subsignal("mosi", Pins("D18")),
+        Subsignal("miso", Pins("D19")),
+        Subsignal("wp",   Pins("G18")),
+        Subsignal("hold", Pins("F18")),
+        IOStandard("LVCMOS25")
+    ),
+
+    # I2C
+    ("i2c", 0,
+        Subsignal("scl", Pins("M1"), Misc("PULLUP=True")),
+        Subsignal("sda", Pins("N1"), Misc("PULLUP=True")),
+        IOStandard("LVCMOS33"),
+    ),
+
+    # GPS.
+    ("gps", 0,
+        Subsignal("pps", Pins("P3"), Misc("PULLDOWN=True")),
+        Subsignal("txd", Pins("N2"), Misc("PULLUP=True")),
+        Subsignal("rxd", Pins("L1"), Misc("PULLUP=True")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # AUX. (Split/Move/Rename?)
+    ("aux", 0,
+        Subsignal("fpga_clk_vctcxo", Pins("N17"), Misc("PULLDOWN=True")),
+        Subsignal("en_tcxo",         Pins("R19"), Misc("PULLUP=True")),
+        Subsignal("ext_clk",         Pins("V17"), Misc("PULLDOWN=True")),
+        Subsignal("en_gps",          Pins("L18")),
+        Subsignal("iovcc_sel",       Pins("V19")),
+        Subsignal("en_smsigio",      Pins("D17")),
+        IOStandard("LVCMOS25")
+    ),
+
+    # RF-Switches / SKY13330, SKY13384.
+    ("rfswitches", 0,
+        Subsignal("tx", Pins("P1"),    Misc("PULLUP=True")),
+        Subsignal("rx", Pins("K3 J3"), Misc("PULLUP=True")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # RF-IC / LMS7002M.
+    ("rfic",
+        # SPI / Control.
+        Subsignal("saen",    Pins("W13")),
+        Subsignal("sdio",    Pins("W16"), Misc("PULLDOWN=True")),
+        Subsignal("sdo",     Pins("W15"), Misc("PULLDOWN=True")),
+        Subsignal("sclk",    Pins("W14")),
+        Subsignal("reset",   Pins("U19")),
+        Subsignal("gpwrdwn", Pins("W17")),
+        Subsignal("rxen",    Pins("W18")),
+        Subsignal("txen",    Pins("W19")),
+
+        # Port1.
+        Subsignal("diq1",   Pins("J19 H17 G17 K17 H19 U16 J17 P19 U17 N19 V15 V16")),
+        Subsignal("txnrx1", Pins("M19")),
+        Subsignal("iqsel1", Pins("P17")),
+        Subsignal("mclk1",  Pins("L17")),
+        Subsignal("fclk1",  Pins("G19")),
+
+        # Port2.
+        Subsignal("diq2",   Pins("W2 U2 V3 V4 V5 W7 V2 W4 U5 V8 U7 U8")),
+        Subsignal("txnrx2", Pins("U4")),
+        Subsignal("iqsel2", Pins("U3")),
+        Subsignal("mclk2",  Pins("W5")),
+        Subsignal("fclk2",  Pins("W6")),
+
+        # IOStandard/Slew Rate.
+        IOStandard("LVCMOS25"),
+        Misc("SLEW=FAST"),
+    ),
 ]
 
 # Platform -----------------------------------------------------------------------------------------